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V30208S Schematic ( PDF Datasheet ) - ETC

Teilenummer V30208S
Beschreibung Ultra Low Power 1-Bit 32 kHz RTC
Hersteller ETC
Logo ETC Logo 




Gesamt 14 Seiten
V30208S Datasheet, Funktion
R
EM MICROELECTRONIC-MARIN SA
Ultra Low Power 1-Bit 32 kHz RTC
V3020
Features
n Supply current typically 390 nA at 3 V
n 50 ns access time with 50 pF load capacitance
n Fully operational from 1.2 V to 5.5 V
n No busy states or danger of a clock update while
accessing
n Serial communication on one line of a standard parallel
data bus or over a conventional 3 wire serial interface
n Interface compatible with both Intel and Motorola
n Seconds, minutes, hours, day of month, month, year, week
day and week number in BCD format
n Leap year and week number correction
n Time set lock mode to prevent unauthorized setting of the
current time or date
n Oscillator stability 0.3 ppm / volt
n No external capacitor needed
n Frequency measurement and test modes
n Temperature range -40 to +85 oC
n On request extended temperature range, -40 to +125 oC
n Pin compatible with the V3021
n TSSO8 and SO8 packages
Description
The V3020 is a low power CMOS real time clock. Data is
transmitted serially as 4 address bits and 8 data bits, over one
line of a standard parallel data bus. The device is accessed by
chip select (CS) with read and write control timing provided by
either RD and WR pulse (Intel CPU) or DS with advanced R/W
(Motorola CPU). Data can also be transmitted over a
conventional 3 wire serial interface having CLK, data I/O and
strobe. The V3020 has no busy states and there is no danger of
a clock update while accessing. Supply current is typically 390
nA at VDD = 3.0 V. Battery operati on is supported by complete
functionality down to 1.2 V. The oscillator s tability is typically 0.3
ppm/V.
Applications
n Utility meters
n Battery operated and portable equipment
n Consumer electronics
n White/brown goods
n Pay phones
n Cash registers
n Personal computers
n Programmable controller systems
n Data loggers
n Automotive systems
Typical Operating Configuration
CPU
Address
Decoder
CS
RD XI
V3020
WR XO
I/O
RAM
CS
RD
WR
Pin Assignment
S08
XI
XO
V3020
CS
VSS
Fig. 1
VDD
WR
RD
I/O
TSSO8
WR
VDD
XI
XO
V3020
RD
I/O
VSS
CS
Fig. 2
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V30208S Datasheet, Funktion
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V3020
Timing Characteristics
VSS = 0 V, and TA = - 40 to + 85 OC, unless otherwise specified
Parameter
Symbol Test Conditions Min. Max. Min. Typ. Max.
VDD ³ 2 V
VDD = 5.0 V ± 10%
Chip select duration
RAM access time1)
Time between two transfers
Rise time2)
Fall time2)
Data valid to Hi-impedance3)
Write data settle time4)
Data hold time5)
Advance write time
Write pulse time6)
tCS
tACC
tW
tR
tF
tDF
tDW
tDH
tADW
tWC
Write cycle
CLOAD = 50pF
500 50
300
500 100
10 200 10
10 200 10
15 200 15
80 50
120 25
20 10
500 50
50
30
1) tACC starts from RD or CS, whichever activates last
Typically, tACC = 5 + 0.9 CEXT in ns; where CEXT (external parasitic capacitance) is in pF
2) CS, RD, DS, WR and R/W rise and fall times are specified by tR and tF
3) tDF starts from RD or CS, whichever deactivates first
4) tDW ends at WR or CS, whichever deactivates first
5) tDH starts from WR or CS, whichever deactivates first
6) tWC starts from WR or CS, whichever activates last and ends at WR or CS, whichever deactivates first
60
200
200
40
Timing Waveforms
Read Timing for Intel (RD and WR Pulse) and Motorola (DS (or RD pin tied to CS) and R/W)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 4
CS
RD / DS
WR / R/W
I/O
tCS
tACC
tR
tDF
data valid
Write Timing for Intel (RD and WR Pulse)
tCS
CS
RD
tWC
WR
tDW tDH
I/O data valid
6
tW
tW
tF
Fig. 7a
Fig. 7b

6 Page









V30208S pdf, datenblatt
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Test
From the various test features added to the V 3020 some may
be activated by the user. Table 7a shows the test mode bits.
Table 8 shows the 3 available test modes and how they can be
activated. Test mode 0 is activated by setting bit 2, address 0,
and causes all time keeping to be accelerated by 32. Test mode
1 is activated by setting bit 3, address 0, and causes all the time
and date locations, address 2 to address 9, to be incremented
in parallel at 1 Hz with no carry over (independent of each
other). The third test mode combines the previous two resulting
in parallel incrementing at 32 Hz.
Test Modes
Addr. 0 Addr. 0
bit 3 bit 2
00
01
10
11
Function
Normal operation
All time keeping accelerated by 32
Parallel increment of all time
data at 1 Hz with no carry over
Parallel increment of all time data
at 32 Hz with no carry over
Table 8
An external signal generator can be used to drive the divider
chain of the V3020. Fig. 13a a nd 13b show how to connect the
signal generator. The speed can be increased by increasing the
signal generator frequency to a maximum of 128 kHz. An
external signal generator and test modes can be combined.
To leave test both test bits (address 0, bits 2 and 3) must be
cleared by software. Test corrupts the current time and date and
so the time and date should be reloaded after a test session.
Signal Generator Connection
XI
1 - 1.5 V peak to peak V3020
XO
VSS
Fig. 13a
Note : The peak value of the signal provided by the signal
generator should not exceed 1.5 V on XO.
V3020
0 - 5.5 V 100 k W1)
36 k W1)
XI
V3020
XO
VSS 1)indicative values
Fig. 13b
Note : The peak value of the signal provided by the signal
generator should not exceed 1.5 V on XO.
Crystal Layout
In order to ensure proper oscillator operation we recommend
the following standard practices.
- Keep traces as short as possible.
- Use a guard ring around the crystal.
Fig. 14 shows the recommended layout.
Oscillator Layout
XI
XO
CS
Vss
V3020
Fig. 14
Access Considerations
The section “Communication Cycles” describes the serial data
sequences necessary to complete a communication cycle. In
common with all serial peripherals, the serial data sequences
are not re-entrant, thus a high priority interrupt, or another
software task, should not attempt to access the V3020 if it is
already in the middle of a cycle. A semaphore (software flag) on
access would allow the V3020 to be shared with other software
tasks or interrupt routines. There is not time limit on the duration
of a communication cycle and thus interrupt routines (which do
not use the V3020) can be fully executed in mid cycle without
any consequences for the V3020.
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