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VP5311BCGGP1N Schematic ( PDF Datasheet ) - Mitel Networks Corporation

Teilenummer VP5311BCGGP1N
Beschreibung NTSC/PAL Digital Video Encoder
Hersteller Mitel Networks Corporation
Logo Mitel Networks Corporation Logo 




Gesamt 19 Seiten
VP5311BCGGP1N Datasheet, Funktion
VP5311B/VP5511B
Supersedes DS4575 1.5 May 1997 version
NTSC/PAL Digital Video Encoder
Advance Information
DS4575 - 2.2 October 1998
The VP5311/VP5511 converts digital Y, Cr, Cb, data
into analog NTSC/PAL composite video and S-video signals.
The outputs are capable of driving doubly terminated 75
ohm loads with standard video levels.
The device accepts data inputs complying with CCIR
Recommendation 601 and 656. The data is time multiplexed
on an 8 bit bus at 27MHz and is formatted as Y, Cr, Y, Cb
(i.e. 4:2:2). The video blanking and sync information from
REC 656 is included in the data stream when the VP5311/
VP5511 is working in slave mode.
The output pixel rate is 27MHz and the input pixel rate
is half this frequency, i.e. 13.5MHz.
All necessary synchronisation signals are generated
internally when the device is operating in master mode. In
slave mode the device will lock to the TRS codes or the HS
and VS inputs.
PIN 64
The rise and fall times of sync, burst envelope and
video blanking are internally controlled to be within
composite video specifications.
Three digital to analog converters (DACs) are used to
convert the digital luminance, chrominance and composite
data into true analog signals. An internally generated
reference voltage provides the biasing for the DACs.
PIN
1
FEATURES
2
s
s
s
s
s
s
s
s
s
s
s
Converts Y, Cr, Cb data to analog composite video and
S-video
www.DataSheet4U.com
Supports CCIR recommendations 601 and 656
All digital video encoding
Selectable master/slave mode for sync signals
Switchable chrominance bandwidth
Switchable pedestal with gain compensation
SMPTE 170M NTSC or CCIR 624 PAL compatible
outputs
GENLOCK mode
Line 21 Closed Caption encoding
I2C bus serial microprocessor interface
VP5311B supports Macrovision anti-taping format Rev.
6.1, in PAL and Rev. 7.01 in NTSC.
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
APPLICATIONS
s Digital Cable TV
s Digital Satellite TV
s Multi-media
s Video games
s Karaoke
s Digital VCRs
18
19
20
21
22
23
24
25
ORDERING INFORMATION
VP5311B/CG/GP1N
VP5511B/CG/GP1N
26
27
28
29
30
31
32
PIN 1 GP64
Figure 1 Pin connections (top view)
FUNCTION
VDD
GND
D0 (VS I/O)
D1 (HS I/O)
D2 (FC0 O/P)
D3 (FC1 O/P)
D4 (FC2 O/P)
D5
D6 (SCSYNC I/P)
D7 (PALID I/P)
GND
VDD
GND
GND
PXCK
VDD
CLAMP
COMPSYNC
GND
VDD
TDO
TDI
TMS
TCK
GND
SA1
SA2
SCL
VDD
SDA
GND
VDD
PIN
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
FUNCTION
VDD
RESET
REFSQ
GND
VDD
GND
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
GND
VDD
AGND
VREF
DACGAIN
COMP
AVDD
LUMAOUT
AGND
COMPOUT
AGND
CHROMAOUT
AVDD
N/C
N/C
AVDD
AVDD
N/C






VP5311BCGGP1N Datasheet, Funktion
VP5311B/VP5511B
REGISTERS MAP
See Register Details for further explanations.
ADDRESS REGISTER
hex NAME
7
6
5
4
3
2
DEFAULT
1 0 R/W hex
BAR
RA7 RA6 RA5 RA4 RA3 RA2
RA1 RA0 W
00 PART ID2 ID17
01 PART ID1 ID0F
02 PART ID0 ID07
03
REV ID
REV7
ID16
ID0E
ID06
REV6
ID15
ID0D
ID05
REV5
ID14
ID0C
ID04
REV4
ID13
ID0B
ID03
REV3
ID12
ID0A
ID02
REV2
ID11
ID09
ID01
REV1
ID10
ID08
ID00
REV0
R
R
R
R
13
66
58
05
04 GCR
-
- YCDELAY RAMPEN SLH&V CVBSCLP VFS1
VFS0
R/W
05 VOCR
- CLAMPDIS CHRBW SYNCDIS BURDIS LUMDIS CHRDIS PEDEN R/W
06 HANC
-
-
DFI2
DFI1
DFI0 Reserved Reserved ACTREN
*
07 ANCID AN7 AN6 AN5 AN4 AN3 AN2
AN1 PARITY R/W
08 SC_ADJ SC7 SC6 SC5 SC4 SC3 SC2
SC1 SC0 R/W
09
FREQ2
FR17
FR16
FR15
FR14
FR13
FR12
FR11
FR10
R/W
0A
FREQ1
FR0F
FR0E
FR0D
FR0C
FR0B
FR0A
FR09
FR08
R/W
0B FREQ0 FR07 FR06 FR05 FR04 FR03 FR02
FR01
FR00
R/W
0C SCHPHM
-
-
-
-
-
-
-
SCH8
R/W
0D SCHPHL SCH7 SCH6 SCH5 SCH4 SCH3 SCH2
SCH1
SCH0
R/W
00
00
00
00
9C
87
C1
F1
00
00
0E to 1F Reserved
20
21
22
23 to EF
F0
F1
F2
F3
F4
F0 to F7
F8
F9
FB
FC
FD
FE
FF
GPPCTL
GPPRD
GPPWR
Not used
CCREG1
CCREG2
CCREG3
CCREG4
CC_CTL
Reserved
HSOFFL
HSOFFM
SLAVE1
SLAVE2
TEST1
TEST2
GPSCTL
CTL7
RD7
WR7
CTL6
RD6
WR6
CTL5
RD5
WR5
CTL4
RD4
WR4
CTL3
RD3
WR3
- F1W1D6 F1W1D5 F1W1D4 F1W1D3
- F1W2D6 F1W2D5 F1W2D4 F1W2D3
- F2W1D6 F2W1D5 F2W1D4 F2W1D3
- F2W2D6 F2W2D5 F2W2D4 F2W2D3
- - - - F2ST
HSOFF7 HSOFF6 HSOFF5 HSOFF4 HSOFF3
- -- - -
NCORSTD VBITDIS VSMODE F_SWAP SL_HS1
HCNT7 HCNT6 HCNT5 HCNT4 HCNT3
REGISTER RESERVED FOR
REGISTER RESERVED FOR
FSC4SEL GENDITH GENLKEN NOLOCK PALIDEN
CTL2
RD2
WR2
F1W1D2
F1W2D2
F2W1D2
F2W2D2
F1ST
HSOFF2
-
SL_HS0
HCNT2
TEST
TEST
TSURST
CTL1
RD1
WR1
CTL0
RD0
WR0
F1W1D1
F1W2D1
F2W1D1
F2W2D1
F2EN
F1W1D0
F1W2D0
F2W1D0
F2W2D0
F1EN
HSOFF1
HSOFF9
HCNT9
HCNT1
HS0FF0
HSOFF8
HCNT8
HCNT0
CHRMCLIP TRSEL
W
R
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FF
-
00
00
00
00
00
00
7E
00
00
00
00
Table.1 Register map
NOTE * For register HANC, bits 3, 4 and 5 are read only. Bits 1 and 2 are reserved. N/A = not applicable.
For register PART ID0 the VP551 value is AB
Standard
Lines/ Field
field freq. Hz
NTSC (default) 525 59.94
PAL-B, G, H, I
625 50
PAL-N (Argentina) 625 50
Number of
pixels/line
at 27MHz
1716
1728
1728
Horizontal
freq. kHz.
fH
15.734266
15.625000
15.625000
Subcarrier
freq. kHz.
fSC
3.57954545
fSC/fH
(455/2)
SC_ADJ
register
hex
xx
4.43361875 (1135/4+1/625) 9C
3.58205625 (917/4+1/625) 57
FREQ2-0
registers hex
87 C1 F1
A8 26 2B
87 DA 51
xx = don’t care.
Table.2 Line, field and subcarrier standards and register settings
The calculation of the FREQ register value is according to the following formula:-
FREQ = 226 x fSC/PXCK hex, where PXCK = 27.00MHz
NTSC value is rounded UP from the decimal number. PAL-B, D, G, H, I and N (Argentina) are rounded DOWN. The SC_ADJ
value is derived from the adjustment needed to be added after 8 fields to ensure accuracy of the Subcarrier frequency. Note the
SC_ADJ value of 9C required for PAL-B, D, G, H, I, is different to the default state of the register.
In NTSC the NCO is reset at the end of every line, this can be disabled by setting the NCORSTD bit in SLAVE1, this allows the
VP5311 to cope with line lengths that are not exactly as specified in REC656.
6

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VP5311BCGGP1N pdf, datenblatt
VP5311B/VP5511B
TIMING INFORMATION
Parameters
Master clock frequency (PXCK input)
PXCX pulse width, HIGH
PXCX pulse width, LOW
PXCX rise time
PXCX fall time
PD7-0 set up time
PD7-0 hold time
SC_SYNC set up time
SC_SYNC hold time
PAL_ID set up time
PAL_ID hold time
PAL_ID duration
Conditions
10% to 90% points
90% to 10% points
Output delay
PXCK to COMPSYNC
PXCK to CLAMP
Note: Timing reference points are at the 50% level. Digital C LOAD <40pF.
Symbol
fPXCK
tPWH; PXCK
tPWL; PXCK
tRP
tFP
tSU;PD
tHD;PD
tSU;SC_SYNC
tHD;SC_SYNC
tSU;PAL_ID
tHD;PAL_ID
tDUR;PAL_ID
tDOS
Min.
10
14.5
10
5
10
0
10
0
9
Typ.
27.0
Max.
TBD
TBD
25
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PXCX
periods
ns
A
HSYNC COLOUR BURST
1
50
0
-40
IRE
B
CLOCK RUN-IN
CD
START BITS
13
H
DATA BYTE 1
E
P
DATA BYTE 2
P
S1 S2 S3 BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7
01000011
FRAME CODE
P = Parity Bit
Figure 7 Closed Capation format
12

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