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PDF VP510CGGPFR Data sheet ( Hoja de datos )
| Número de pieza | VP510CGGPFR | |
| Descripción | Bi Directional Colour Space Converter | |
| Fabricantes | Zarlink Semiconductor Inc | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de VP510CGGPFR (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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This information is available for your
convenience only.
For more information on
Zarlink’s obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
1 page  
VP 510
filter with 13.5 MHz output sampling.
CHROMINANCE FILTERS
Each chrominance channel has two 11 tap filters in series
and each pair can decimate or interpolate by four. The MODE
bit defines whether the filters interpolate or decimate. The
coefficients are 10 bit internally defined values, and are the
same in both modes. Figure 4 illustrates the bit significance at
various points in the calculation.
When the filters are used to decimate chrominance pro-
duced by the matrix converter, the inputs are represents by
either 8 or 9 signed integer bits plus 3 fractional bits. When the
matrix coefficients have been chosen to produce normalized
chrominance, the range can be represented by 8 integer bits.
Otherwise 9 integer bits are needed. When the inputs are
chrominance from the pins, the 3 fractional bits are set to zero,
and the ninth bit is sign extended. Words within the filter
calculation are allowed to grow to 15 integer bits plus 6
fractional bits. This is then rounded to 15 bits plus 3 fractional
bits.
When the filter is used to supply interpolated data to the
matrix converter, the least significant 10 integer bits are
selected out of the 15 outputs. Only 9 integer bits are actually
needed to represent the filtered chrominance with undershoot
and overshoot, but the hardware multiplier expects a 10 bit
number.
When the filter is producing decimated chrominance, the
NORM bit in the Control Register is used to select which 12
integer and fractional bits will be used by the rounding and
clipping circuit. For a full description of this operation see the
section on Chrominance Outputs.
The response of the filters is given in Figure 5. These
results were obtained with 10 bit quantized coefficients and
unquantized data. The effects of the various quantization
steps within the filter, and then finally rounding down to a 9 bit
value are superimposed onto Figure 5. Also shown is the
CCIR601 specification for sample rate conversion down to
4:2:2 resolution.
RGB INPUTS
The 24 bit RGB data must meet the set up and hold
requirements, with respect to the rising edge of the clock,
which are specified in Figure 6. The first edge after HREF has
gone inactive ( i.e. high ) must strobe in the first samples if the
delay to the first correctly filtered output is to match the fixed
pipline delay of 39 clock to the HDLY and FO outputs. The
maximum range is 0 to 255 for each component. If the
coefficients in the matrix converter are defined for a restricted
input range then this must be guaranteed by the user. Alterna-
tively the look up tables can be used to limit the range. When
HREF goes active low the outputs will go low after 39 clocks.
The VP510 has been designed to accept two times over-
sampled RGB data from an A/D converter. This avoids the
need for analog anti aliasing filters before the A/D converters.
For this reason the clock used by the VP510 is expected to be
twice the sampling clock needed to produce a given number
of RGB pixels per line. If the RGB inputs have not been
oversampled this double rate clock should still be used. Each
incoming sample will then be internally used twice, but the
decimating filters will still produce the correct luminance and
chrominance values.
Each input directly addresses its own RAM, which has
been pre-loaded to meet the system requirements. Linear
NORMALIZED FREQUENCY
RGB
From
Pins
From
Matrix
0.1 0.2 0.3 0.4 0.5
0
8.000
8.3 Normalized
9.3 Un - normalized
Coefficents
1.9
TWO MAC
ARRAYS
15.6
ROUND
15.3
10.3
To Matrix
Converter
in Interpolate
Mode
SELECT 10 LS
INTEGER BITS
(NO FRACTIONAL)
10.0
ROUND
WITH LSB
9
SELECT 9 LS
INTEGER BITS
+ MS FRACTIONAL
9.1
ROUND WITH
MS FRACTIONAL
9
NORM CONTROL
BIT
10
20
30
40 0.15
CCIR601 Specification
Quantized Coefficients, FP data
Quantized Coefficients and Data
Peak 0.25 dB
50 0.1
60 0.05
70 0.0
0.05
0.1 0.15
CLIP TO 8 BITS
Signed 8.0 to Pins
80 -0.05
-0.1
PASSBAND RIPPLE
Figure 4. Bit significance
4
Figure 5. Response of the Chrominance Filters
5 Page 
VP 510
250
RED CHANNEL
200
150
100
50
GREEN OR BLUE CHANNEL
0
5 10 15 20
0
5 10 15 20 25
27 MHZ CLOCK PERIODS
Figure 10. RGB Response to step changes in Y Cr Cb
RESPONSE TO INPUT STEP CHANGES
Figure 10 shows the actual response given by the RGB
outputs to step changes in the Y Cr Cb inputs. Note that both
negative undershoot and overshoot above 255 are prevented
by the clipping circuit. The response of the Blue and Green
filters will always be identical since they use identical circuits.
The Red channel uses a different interpolating filter.
The Y Cr Cb changes were calculated to theoretically
cause the RGB outputs to swing from maximum to minimum
values, using the analog coefficients. Initial Y Cr Cb values
were 151/20/43 with a step to 105/236/213. These should
cause RGB to change from 0/255/0 to 255/0/255. The second
transition was caused by changing the Y CR Cb values from
228/148/0 to 179/0/171. This should cause RGB to change
from 255/255/0 to 0/255/255.
Figure 11 show the response of the Y Cr Cb outputs to
maximum range step changes in RGB. The sequence used to
cause the four transitions, and the theoretical results are given
below.
RG B
Y Cr Cb
Start 255 255 255
T1 255 255 0
T2 0
255 255
T3 0
255 0
T4 255 0
255
235 128 128
226 149 16
178 16 172
148 21 44
106 237 212
250 TRANSITION 1
TRANSITION 2
Y
200
TRANSITION 3
TRANSITION 4
Cr
Cb
Cr
150
Y
100
50
0
10
Cb
5 10 15 20 25 30 35 40 45 50
13.5 MHZ CLOCK PERIODS
Figure 11. Y Cr Cb response to step changes in RGB
11 Page | ||
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