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PDF VP2611CGGH1R Data sheet ( Hoja de datos )
| Número de pieza | VP2611CGGH1R | |
| Descripción | H.261 Encoder | |
| Fabricantes | Mitel Networks Corporation | |
| Logotipo |  |
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Supersedes June 1996 edition, DS3487 - 4.0
VP2611
VP2611
H.261 Encoder
DS3487 - 4.1 December 1998
FEATURES
s Fully integrated H261 video encoder
s Up to full CIF resolution and 30 Hz frame rates
s Inputs YUV data in 8 x 8 sub block format
s Outputs run length coded coefficients
s On chip motion vector estimator with +/-7 pixel search
window
s Addresses and control generated internally for DRAM
frame store
s QFP package
ASSOCIATED PRODUCTS
s VP510 Colour Space Converter
s VP520S CIF/QCIF Converter
s VP2612 Video Multiplexer
s VP2614 Video Demultiplexer
s VP2615 H.261 Decoder
DESCRIPTION
The VP2611 Video Compression Source Coder forms part
of a chip set used in video conferencing, video telephony and
multimedia applications. It produces data which conforms to
the H261 standard for video compression with rates between
64K and 2M bits per second. With a 27 MHz clock the device
will accept data produced to full CIF resolution at 30 Hz frame
rates. The pipeline latency through the device is only 3 macro
block periods.
The VP2611 contains all the elements necessary for the
compression algorithm. It incorporates a Motion Vector Esti-
mator which performs a +/- 7 pixel search. The decision to use
inter or intra frame compression is made by the device, and the
selected data blocks are read from the frame store. New or
difference data is then passed through a Discrete Cosine
Transformer and quantized. Data from the quantizer is also
inverse quantized and passed through an Inverse Discrete
Cosine Transformer. This re-constructed data is then written
to the frame store for use in the next frame period.This frame
store is managed by an internal DRAM controller, and no
external logic is needed.
The input data must be in YUV space, and must also
conform to the six sub blocks per macro block format defined
by H261. Any conversion from RGB format is performed by
the VP510 Colour Space Converter. Any reduction in spatial
resolution, down to CIF or QCIF requirements, is done by the
VP520 Three Channel Video Filter.
The quantized data is zig-zag scanned and run length
coded before being output, together with block information
and motion vectors.
R VP510
G COLOUR SPACE
CONVERTER
B
NTSC
PAL
COMP VIDEO
DECODER
VIDEO
SYNC
USER
INTERFACE
Y
Cr/Cb
VP520
3 CHANNEL
VIDEO FILTER
REQYUV
FRMIN
MBLK'S
ADDR
DATA
CIF FRAME
STORE
16 X128K
SYSTEM
CONTROLLER
VP2611
RLC DATA
INTEGRATED
VIDEO ENCODER FLAGS
CIF FRAME
STORE
16X128K
CCIR601 RESOLUTION
Y 720 X 288 Cr/Cb 360 x 288
Y 720 X 240 Cr/Cb 360 x 240
NTSC
PAL
CIF RESOLUTION
Y 352 X 288
Cr/Cb 176 x 144
VP2612
VIDEO
MULTIPLEXER
TX BUFFER
32K X 8
H261
BIT
STREAM
64kb to 2Mb/s
Fig 1 : Typical Video Conferencing Transmission System
1
1 page  
VP2611
YUV Input
Frame Store Read
Control Decisions
Frame Store Write
DBUS Output
2064 cycles
MB1
MB2
MB3
DUMMY
MB1
MB2
DUMMY
MB1
MB2
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
MB4
MB3
MB3
MB1
MB1
Fig 4: MacroBlock Pipelining
SUBBLOCK ORDER WITHIN MACROBLOCK
12
56
34
U
V
Y
OPERATION OF INTERFACES
PIXEL ORDER WITHIN SUBBLOCK
Macroblock Delays
The VP2611 has a three macroblock pipeline delay be-
tween pixel inputs and run length coded outputs. This is
illustrated in Figure 4. Whilst the second macroblock is being
input, the best fit macroblock from the previous frame is being
identified and then read from the frame store. At this time any
Control Decisions which are to effect the first macroblock must
be supplied by the host controller. The run length coded
outputs for the first macroblock are not available until the
fourth macroblock is supplied at the input pins.
YUV Input Port
The YUV port accepts pixel data from the preprocessor in
block format as illustrated in Figure 5. Within a complete
system the VP2611 is always the master device, and must be
supplied with macroblock data when it makes a demand. The
order in which pixels are supplied is pre-determined, and must
be strictly maintained. There are 64 pixels per sub-block and
4 luminance and 2 chrominance sub-blocks per macroblock.
The macroblocks themselves are divided into groups of blocks
( GOB's ), and the sequence specified in H.261 must also be
maintained. Note that, since the chrominance resolution is half
the luminance resolution both vertically and horizontally, then
the two chrominance blocks cover the same picture area as
the four luminance blocks.
The pre-processor producing macroblock data must pro-
duce a frame start signal ( FRMIN ) when it has a complete
frame of data available. This resets the input controller within
the VP2611, which will then generate sequential GOB and
macroblock numbers for the coded outputs referenced to this
input.
FRMIN must go high for at least one system clock period,
and must go low before the next frame is available. The
VP2611 responds to FRMIN with a request for macroblock
data ( REQYUV ), which occurs approximately 184 SYSCLK
periods after FRMIN. It must then receive a complete macrob-
lock within 1871 SYSCLK periods, and at the end of this time
REQYUV will go inactive. The VP2611 must be provided with
a PCLK signal to strobe in the data. This must be derived from
SYSCLK, and must only be present when there is valid data
at the input. Data must meet the set up and hold times with
respect to PCLK as specified in Figure 6.
The maximum peak rate for PCLK is the SYSCLK rate
divided by two, but since there are 384 bytes per macroblock
00 01 02 03 04 05 06 07
08 09 10 11 12 13 14 15
16 17 18 0139 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
Fig 5 : Ordering of Pixels
then theoretically the average rate need only be 384/1871
times the SYSCLK rate. Note that PCLK must always be
obtained by dividing SYSCLK by an integer greater than one.
When the VP520 CIF/QCIF Converter is supplying the VP2611
with data, it provides a peak PCLK rate equivalent to SYSCLK
divided by two, and an average rate of SYSCLK divided by
four.
The mimimum gap between REQYUV going active is
2064 SYSCLK periods. In full CIF mode "dummy" macrob-
locks are internally inserted between rows, in order to give the
chip sufficient time to load a new search window. No new YUV
data must be loaded during these dummy macroblocks, and
REQYUV will remain inactive. No dummy macroblocks are
required in QCIF mode. With a 27MHz SYSCLK all macrob-
locks will be coded in less than a 30Hz frame rate period, and
there will be a period of inactivity before FRMIN goes active
again. During this period the output bus will remain static at all
ones, and no output strobe ( DCLK ) will be produced.
PCLK
YUV7:0
10ns
20ns
0ns
SCLK/2
20ns
N.B. All timings given are MINIMUM values.
Fig 6 : Timing at YUV Port
5
5 Page 
ABSOLUTE MAXIMUM RATINGS [See Notes]
Supply voltage VDD
-0.5V to 7.0V
Input voltage VIN
-0.5V to VDD+ 0.5V
Output voltage V
-0.5V to VDD + 0.5V
OUT
Clamp diode current per pin I (see note 2)
18mA
K
Static discharge voltage (HBM)
500V
Storage temperature T
S
-55°C to 150°C
Ambient temperature with power applied T
AMB
0°C to 70°C
Junction temperature
125°C
Package power dissipation
3000mW
NOTES ON MAXIMUM RATINGS
1. Exceeding these ratings may cause permanent damage.
Functional operation under these conditions is not implied.
2. Maximum dissipation for 1 second should not be exceeded,
only one output to be tested at any one time.
3. Exposure to absolute maximum ratings for extended
periods may affect device reliablity.
4. Current is defined as negative into the device.
VP2611
STATIC ELECTRICAL CHARACTERISTICS
Operating Conditions (unless otherwise stated)
Tamb = 0 C to +70°C VDD = 5.0v ± 5%
Characteristic
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input leakage current
Input capacitance
Output leakage current
Output S/C current
Symbol
V
OH
V
OL
V
IH
VIL
IIN
CIN
IOZ
ISC
Value
Min. Typ. Max.
2.4 -
- 0.4
2.0 -
- 0.8
-10 +10
10
-50 +50
10 300
Units
V
V
V
V
µA
pF
µA
mA
Conditions
IOH = 4mA
IOL = -4mA
V -1V for SYSCLK and PCLK
DD
GND < V < V
IN DD
GND < V < V
OUT
DD
V = Max
DD
ORDERING INFORMATION
VP2611 CG GH1R (Commercial - Plastic QFP power package)
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet VP2611CGGH1R.PDF ] | |
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