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VP215 Schematic ( PDF Datasheet ) - Mitel Networks Corporation

Teilenummer VP215
Beschreibung Dual 90MHz 6-Bit Analog to Digital Converter
Hersteller Mitel Networks Corporation
Logo Mitel Networks Corporation Logo 




Gesamt 7 Seiten
VP215 Datasheet, Funktion
VP215
Dual 90MHz 6-Bit Analog to Digital Converter
Preliminary Information
DS4068 - 1.4 May 1996
The VP215 is a dual 90MHz 6-bit Analog to Digital
Converter designed for use in consumer satellite receivers
and decoders, video systems, multimedia and
communications applications.
Operating from a single +5V supply, the VP215 includes
an on-chip high bandwidth ADC driver amplifier, a 6-bit ADC
and digital I/O that can be interfaced to either +5V or +3V.
The VP215 also has the necessary bias voltages for the
reference resistor chain in the 'flash' architecture of the ADC.
FEATURES
s 90MHz Conversion Rate
s TTL Clock/Data Interface
s 0.5 Volt Analog Input Range
s Internal ADC Reference
s Digital I/O’s compatible with +5V or +3V logic
s Single 5 Volt Supply
s Dual ADC System for good channel matching
APPLICATIONS
s Satellite Decoders
s Multimedia
s Communications
www.DataSheet4U.com
ORDERING INFORMATION
VP215A CG MP1S (Commercial - 28 pin plastic SO)
CLKIN
VCCD
DGND
VRT
COMPA
VINA
AGND
VCCA
VRM
COMPB
VINB
VRB
N.C.
N.C.
1
2
3
4
5
6
7
8 VP215
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DA5
DA4
DA3
DA2
DA1
DA0
OGND
VCCO
DB5
DB4
DB3
DB2
DB1
DB0
MP28
Fig.1 Pin connections - top view (wide body)
--------V-CC-D--------------VC-C-A --------------VC-CO--------
28
21
5
COMPA
6
VINA
9
VRM
ADC
DRIVER
+
6-BIT
ADC
VRB VRM VRT
6 LATCHES
DATA
OUTPUTS
23 DA0
24 DA1
25 DA2
26 DA3
27 DA4
28 DA5
VRB 12
VREF
OP AMPS
CLOCK
DRIVER
1
CLKIN
VRT 4
VINB 11
COMPB
10
+
ADC
DRIVER
VRB VRM VRT
6-BIT
ADC
LATCHES
6
DATA
OUTPUTS
15 DB0
16 DB1
17 DB2
18 DB3
19 DB4
20 DB5
----------3----------------7---------------2-2-------
DGND
AGND
OGND
Fig.2 System block diagram






VP215 Datasheet, Funktion
VP215
Layout And Grounding
As with all high speed A to D converters, careful
consideration must be given to the PCB layout. High
performance can be obtained from the VP215 by tying all
grounds to a solid low impedance ground plane. Separate
analog and digital ground planes with a single common link
under the device can also be used to help reduce the
amount of digital noise fed back into the analog section of the
converter.
The VP215 should be decoupled with low impedance
100nF ceramic capacitors close to the package pins to avoid
lead inductance effects and the decoupling on supply lines
should further be improved by using a 47µF tantalum
capacitor in parallel with a 100nF ceramic capacitor. If VCCA
is derived from VCCD, a small inductor should be used to
reduce digital noise on the analog power supply. Jitter and
noise on clock input pins must be minimised. Long clock
lines should therefore be avoided and all clock lines correctly
terminated. Cross talk of digital signals to the analog inputs
must also be prevented as sampling cross talk produces DC
offsets on the sampled data, for this reason analog inputs
should not be run next to clock or data lines. Device
connections to the ground plane should be as short as
possible.
CLKIN
50R 1.2µH
VINA
VCCA
47µ
VINB
Cc
50R
100n
Cc
50R
1
100n
2
3
100n
Ccomp
4
5
6
VP215
7
100n
Ccomp
8
9
100n
10
11
100n
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A Channel
Data
100n
47µ
B Channel
Data
VCCD
100n
Analog Ground
Digital Ground
Fig.5 Applications diagram
Application Circuit
Fig.5 shows a typical applications circuit for the VP215.
The supply connections are made using separate low noise
digital and analog power supplies and VCCD is further
isolated from VCCO using a 1.2µH inductor.
The COMPA and COMPB pins must be decoupled to
reduce any ripple at low frequencies which may distort the
ADC driver amplifier output, (see Fig.2.) The decoupling
capacitor value is determined by the required low frequency
performance of the system and can be obtained from the
following equation.
CComp = 75x10- 6
Fin x VRipple
A ripple voltage 10mV is recommended for good
system performance, e.g. If the analog input frequency Fin=
10KHz a value of 0.75µF is required for CComp.
To ensure effective A.C. coupling at low input
frequencies, the coupling capacitors on pins 6 and 11 can be
calculated from the high pass filter corner frequency
equation,
Fc =
1
2 x π x RC
where
Fc = Lower -3dB corner frequency
(R = Input Resistance, 25K typ. - 20K min)
6

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