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VP101-5BADP Schematic ( PDF Datasheet ) - Zarlink Semiconductor Inc

Teilenummer VP101-5BADP
Beschreibung 30/50MHz 8-BIT CMOS VIDEO DAC
Hersteller Zarlink Semiconductor Inc
Logo Zarlink Semiconductor Inc Logo 




Gesamt 10 Seiten
VP101-5BADP Datasheet, Funktion
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THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
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VP101-5BADP Datasheet, Funktion
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VP101
Pin name
Description
BLANK
SYNC
Composite blank control input. A logic ‘0’ forces the IOR, IOG and IOB outputs to the blanking level, as
illustrated in Table 1. It is latched on the rising edge of CLOCK. When BLANK is a logic zero, the R0-R7, G0-
G7, B0-B7, and REF WHITE inputs are ignored.
Composite sync control input. A logic ‘0’ on this input switches off a 40 IRE current source on the ISYNC
output. SYNC does not override any other control or data input as shown in Table 1; therefore it should be
asserted only during the blanking interval. It is latched to the rising edge of CLOCK.
REF
WHITE
R0-R7
G0-G7
B0-B7
CLOCK
Reference white level control input. A logic ‘1’ on this input forces the IOR, IOG and IOB outputs to the white
level, regardless of the R0-R7, G0-G7 and B0-B7 inputs. It is latched on the rising edge of CLOCK. See table 1.
Red, Green, and Blue data inputs. R0, G0, and B0 are the least significant data bits. They are latched on the
rising edge of CLOCK. Coding is binary. Unused inputs should be connected to either the regular PCB power
or ground plane.
Clock input. The rising edge of CLOCK latches the R0-R7, G0-G7 and B0-B7 SYNC, BLANK, and REFWHITE
inputs. It is typically the pixel clock rate of the video system. It is recommended that the CLOCK input be
driven by a dedicated CMOS buffer.
IOR,IOG,
IOB
ISYNC
FS
ADJUST
Red, Green, and Blue current outputs. these high impedance current sources are capable of directly driving a
doubly terminated 75co-axial cable. All outputs, whether used or not, should have the same output load
(Note: A DC path to ground must be maintained).
Sync current output. Typically this current output is directly wired to the IOG output, and enables sync
information to be encoded onto the green channel. A logic ‘0’ on the SYNC input results in no current being
output to this pin, while logic ‘1’ results in the following current being output:
ISYNC (mA) = 3468 X VR−−RSEEFT((VΩ−)) 111 LSBs
If sync information is not required on the green channel, this output may be connected to VAA and the SYNC
input tied high, causing the ISYNC current source to be turned off, reducing the power consumption.
www.DataSheet4U.comFull scale adjust control. A resistor (RSET) connected between this pin and AGND controls the magnitude of
the full video signal (Fig. 3). The current flowing in the RSET resistor is equal to 32 LSBs. note that the IRE
relationships in Fig. 3 are maintained, regardless of the full scale output current.
The relationship between RSET and full scale current on IOG (assuming ISYNC is connected to IOG) is:
IOG (mA) = 12082 X VRRSEEFT((VΩ−)) 387 LSBs
The full scale output current on IOR, IOB (mA) for a given RSET is defined as:
IOR, IOB (mA) = 8624 X VRRSEEFT((VΩ−))276 LSBs
COMP
Compensation pin. This pin provides compensation for the internal loop amplifier. A 0.01µF ceramic capacitor must
be connected between this pin and the nearest VAA pin.
Connecting the capacitor to VAA rather than to the AGND provides the highest possible power supply noise
rejection.
VREF
AGND
VAA
Voltage reference output. The output from an internal reference circuit, providing 1.2V (typical) reference.A
0.1µF ceramic capacitor must be used to decouple this output to VAA.
Analog ground. All AGND pins must be connected.
Analog power. All VAA pins must be connected.
5
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