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VIPer20A Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer VIPer20A
Beschreibung SMPS PRIMARY I.C.
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 21 Seiten
VIPer20A Datasheet, Funktion
VIPer20/SP/DIP
® VIPer20A/ASP/ADIP
SMPS PRIMARY I.C.
TYPE
VIPer20/SP/DIP
V I Per2 0A/ A SP/ AD IP
V DSS
6 20V
7 00V
In
0.5 A
0.5 A
RDS(on)
16
18
FEATURE
s ADJUSTABLE SWITCHING FREQUENCY UP
TO 200KHZ
s CURRENT MODE CONTROL
s SOFT START AND SHUT DOWN CONTROL
s AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
”BLUE ANGEL” NORM (<1W TOTAL POWER
CONSUMPTION)
s INTERNALLY TRIMMED ZENER
REFERENCE
s UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
s INTEGRATED START-UP SUPPLY
s AVALANCHE RUGGED
s OVERTEMPERATURE PROTECTION
s LOW STAND-BY CURRENT
s ADJUSTABLE CURRENT LIMITATION
DESCRIPTION
VIPer20/20A, made
BLOCK DIAGRAM
using
VIPower
M0
PENTAWATT HV PENTAWATT HV (022Y)
10
1
PowerSO-10
DIP-8
Technology, combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized high voltage avalanche rugged Vertical
Power MOSFET (620V or 700V / 0.5A).
Typical applications cover off line power supplies
with a secondary power capability of 10W in wide
range condition and 20W in single range or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50% less components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the possibility to operate in stand-by
mode without extra components.
OSC
DRAIN
November 1999
VDD
ON/OFF
OSCILLATOR
UVLO
LOGIC
SECURITY
LATCH
R/S FF Q
S
PWM
LATCH
S
R1 FF Q
R2 R3
OVERTEMP.
DETECTOR
0.5 V
ERROR
AMPLIFIER
_
+
_
13 V +
4.5V
1.7
µs
delay
250 ns
Blanking
COMP
0.5V
++ _
6 V/A
_
CURRENT
AMPLIFIER
SOURCE
1/21






VIPer20A Datasheet, Funktion
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 1: VDD Regulation Point
ICOMP
ICOMPHI
Slope =
Gm in mA/V
VDD
0
ICOMPLO
VDDreg
FC00150
Figure 3: Transition Time
ID
VDS
10% Ipeak
90% VD
t
10% VD
tf
t
tr
FC00160
Figure 5: Breakdown Voltage vs Temperature
1.15
BVDS S
(Nor malize d)
1.1
FC0 0180
1.05
1
0.95
0
20 40 60 80 100 120
Temp erature ( C)
Figure 2: Undervoltage Lockout
IDD
IDD0
IDDch
VDDhyst
VDDoff
VDS = 70 V
Fsw = 0
VVDDon
DD
FC00170
Figure 4: Shut Down Action
VOS C
VCOMP
VCOMPth
ID
tDIS s u
t
t
ENABLE
t
ENABLE
DISABLE
FC 00 0 6 0
Figure 6: Typical Frequency Variation
1
(%)
0
FC0 019 0
-1
-2
-3
-4
-5
0 20 40 60 80 100 120 140
Temperature ( C)
6/21

6 Page









VIPer20A pdf, datenblatt
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
OPERATION DESCRIPTION :
CURRENT MODE TOPOLOGY:
The current mode control method, like the one
integrated in the VIPer20/20A uses two control
loops - an inner current control loop and an outer
loop for voltage control. When the Power
MOSFET output transistor is on, the inductor
current (primary side of the transformer) is
monitored with a SenseFET technique and
converted into a voltage VS proportional to this
current. When VS reaches VCOMP (the amplified
output voltage error) the power switch is switched
off. Thus, the outer voltage control loop defines
the level at which the inner loop regulates peak
current through the power switch and the primary
winding of the transformer.
Excellent open loop D.C. and dynamic line
regulation is ensured due to the inherent input
voltage feedforward characteristic of the current
mode control. This results in an improved line
regulation, instantaneous correction to line
changes and better stability for the voltage
regulation loop.
Current mode topology also ensures good
limitation in the case of short circuit. During a first
phase the output current increases slowly
following the dynamic of the regulation loop. Then
it reaches the maximum limitation current
internally set and finally stops because the power
supply on VDD is no longer correct. For specific
applications the maximum peak current internally
set can be overridden by externally limiting the
voltage excursion on the COMP pin. An
integrated blanking filter inhibits the PWM
comparator output for a short time after the
integrated Power MOSFET is switched on. This
function prevents anomalous or premature
termination of the switching pulse in the case of
current spikes caused by primary side
capacitance or secondary side rectifier reverse
recovery time.
STAND-BY MODE
Stand-by operation in nearly open load condition
automatically leads to a burst mode operation
allowing voltage regulation on the secondary
side. The transition from normal operation to
burst mode operation happens for a power PSTBY
given by :
PSTBY
=
1
2
LP
IS2 TBY
FSW
Where:
LP is the primary inductance of the transformer.
FSW is the normal switching frequency.
ISTBY is the minimum controllable current,
corresponding to the minimum on time that the
device is able to provide in normal operation. This
current can be computed as :
ISTBY
=
(tb
+ td)
LP
VIN
tb + td is the sum of the blanking time and of the
propagation time of the internal current sense
and comparator, and represents roughly the
minimum on time of the device. Note that PSTBY
may be affected by the efficiency of the converter
at low load, and must include the power drawn on
the primary auxiliary voltage.
As soon as the power goes below this limit, the
auxiliary secondary voltage starts to increase
above the 13V regulation level forcing the output
voltage of the transconductance amplifier to low
state (VCOMP < VCOMPth). This situation leads to
the shutdown mode where the power switch is
maintained in the off state, resulting in missing
cycles and zero duty cycle. As soon as VDD gets
back to the regulation level and the VCOMPth
threshold is reached, the device operates again.
The above cycle repeats indefinitely, providing a
burst mode of which the effective duty cycle is
much lower than the minimum one when in
normal operation. The equivalent switching
frequency is also lower than the normal one,
leading to a reduced consumption on the input
mains lines. This mode of operation allows the
VIPer20/20A to meet the new German ”Blue
Angel” Norm with less than 1W total power
consumption for the system when working in
stand-by. The output voltage remains regulated
around the normal level, with a low frequency
ripple corresponding to the burst mode. The
amplitude of this ripple is low, because of the
output capacitors and of the low output current
drawn in such conditions.The normal operation
resumes automatically when the power get back
to higher levels than PSTBY.
HIGH VOLTAGE START-UP CURRENT
SOURCE
An integrated high voltage current source
provides a bias current from the DRAIN pin
during the start-up phase. This current is partially
absorbed by internal control circuits which are
12/21

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