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VIC068A-UMB Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer VIC068A-UMB
Beschreibung VMEbus Interface Controller
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 15 Seiten
VIC068A-UMB Datasheet, Funktion
VIC068A
Features
• Complete VMEbus interface controller and arbiter
— 58 internal registers provide configuration control
and status of VMEbus and local operations
— Drives arbitration, interrupt, address modifier utility,
strobe, address lines A07 through A01 and data lines
D07 through D00 directly, and provides signals for
control logic to drive remaining address and data
lines
— Direct connection to 68xxx family and mappable to
non-68xxx processors
Complete master/slave capability
— Supports read, write, write posting, and block trans-
fers
— Accommodates VMEbus timing requirements with
internal digital delay line (12-clock granularity)
— Programmable metastability delay
— Programmable data acquisition delays
— Provides timeout timers for local bus and VMEbus
transactions
Interleaved block transfers over VMEbus
— Acts as DMA master on local bus
— Programmable burst count, transfer length, and in-
terleaved period interval
— Supports local module-based DMA
Arbitration support
— Supports single-level, priority and round robin arbi-
tration
— Supports fair request option as requester
Interrupt support
— Complete support for the VMEbus interrupts: inter-
rupter and interrupt handler
VMEbus Interface Controller
— Seven local interrupt lines
— 8-level interrupt priority encode
— Total of 29 interrupts mapped through the VIC068A
Miscellaneous features
— Refresh option for local DRAM
— Four broadcast location monitors
— Four module-specific location monitors
— Eight interprocessor communications registers
— PGA or QFP packages
— Compatible with IEEE Specification 1014, Rev. C
— Supports RMC operations
See the VMEbus Interface Handbook for more informa-
tion
Functional Description
The VMEbus interface controller (VIC068A) is a single chip
designed to minimize the cost and board area requirements
and to maximize performance of the VMEbus interface of a
VMEbus master/slave module. This can be implemented on
VIC068A either an 8-bit, 16-bit, or 32-bit VMEbus system. The
VIC068A performs all VMEbus system controller functions
plus many others, which simplify the development of
VIC068Aa VMEbus interface. The VIC068A utilizes patented
on-chip output buffers. These CMOS high-drive buffers pro-
vide direct connection to the address and data lines. In addi-
tion to these signals, the VIC068A connects directly to the ar-
bitration, interrupt, address modifier, utility and strobe lines.
Signals are provided which control data direction and latch
functions needed for a 32-bit implementation.
The VIC068A was developed through the efforts of a consor-
tium of board vendors, under the auspices of the VMEbus In-
ternational Trade Association (VITA). The VIC068A thus in-
sures compatibility between boards designed by different
manufacturers.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1990 - Revised July 23, 1997






VIC068A-UMB Datasheet, Funktion
VIC068A on 68030 Board
VIC068A
512/256K X 36 DRAM
512/256K X 36 DRAM
32
Latching Transceivers
Address
Mux
32
Latching Transceivers
LD0 –LD31
Parity Check
Logic
68030
LA0 –LA 31
4 JEDEC EPROMs
EPROM
Map Decoder VMEbus
DRAM I/O
MWB*
WORD*
ASIZ1
ASIZ0
FCT
543
FCT
543
FCT
245
FCT
245
FCT
245
FCT
543
D24–D31
D16–D23
D 08–D16
FCT
543
A31–A24
ISOBE*
FCT
543
A23–16
FCT
245 LD0 –LD7
VIC068A
FCT
543
LA0 –LA7
W1 SCON*
Slave
Select
Decode
SLSEL0*
SLSEL1*
ICFSEL
A15–A08
LIACKO* LIRQ1* - LIRQ7*
A1 – A 7
SYSCLK
D00 –D07
AM 0 – AM 5
AS*, DS0*, DS1*, DTACK*,
WRITE*, LWORD*, BERR*
BGiIN*, BGiOUT*, BRi*, BBSY*
IACK*, IACKIN*, IACKOUT*
IRQ1*, IRQ7*, ACFAIL*,
SYSFAIL*
STSRESET*
VIC068A–4
6

6 Page









VIC068A-UMB pdf, datenblatt
Package Diagrams (continued)
145-Pin Plastic Grid Array (CavityUp) B144
VIC068A
12

12 Page





SeitenGesamt 15 Seiten
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