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X76F640W-2.7 Schematic ( PDF Datasheet ) - Xicor

Teilenummer X76F640W-2.7
Beschreibung Secure SerialFlash
Hersteller Xicor
Logo Xicor Logo 




Gesamt 17 Seiten
X76F640W-2.7 Datasheet, Funktion
64K
X76F640
8Kx8+32x8
Secure SerialFlash
FEATURES
• 64-bit Password Security
—Five 64-bit Passwords for Read, Program
and Reset
• 8192 Byte+32 Byte Password Protected Arrays
—Seperate Read Passwords
—Seperate Write Passwords
—Reset Password
• Programmable Passwords
• Retry Counter Register
—Allows 8 tries before clearing of both arrays
—Password Protected Reset
• 32-bit Response to Reset (RST Input)
• 32 byte Sector Program
• 400kHz Clock Rate
• 2 wire Serial Interface
• Low Power CMOS
—2.7 to 5.5V operation
—Standby current Less than 1µA
—Active current less than 3 mA
• High Reliability Endurance:
—100,000 Write Cycles
• Data Retention: 100 years
• Available in:
—8 lead SOIC
—SmartCard Module
DESCRIPTION
The X76F640 is a Password Access Security Supervisor,
containing one 65536-bit Secure SerialFlash array and
one 256-bit Secure SerialFlash array. Access to each
memory array is controlled by two 64-bit passwords.
These passwords protect read and write operations of
the memory array. A separate RESET password is used
to reset the passwords and clear the memory arrays in
the event the read and write passwords are lost.
The X76F640 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA). Access to the device
is controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X76F640 also features a synchronous response to
reset providing an automatic output of a hard-wired 32-bit
data stream conforming to the industry standard for
memory cards.
The X76F640 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
Functional Diagram
CS
SCL
SDA
INTERFACE
LOGIC
RST
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7025-1.4 3/24/97 T2/C0/D1 SH
CHIP ENABLE
DATA TRANSFER
ARRAY ACCESS
ENABLE
PASSWORD ARRAY
AND PASSWORD
VERIFICATION LOGIC
RESET
RESPONSE REGISTER
1
8K BYTE
SerialFlash ARRAY
ARRAY 0
(PASSWORD PROTECTED)
32 BYTE
SerialFlash ARRAY
ARRAY 1
(PASSWORD PROTECTED)
RETRY COUNTER
7025 FM 01
Characteristics subject to change without notice






X76F640W-2.7 Datasheet, Funktion
X76F640
ACK Polling
Once a stop condition is issued to indicate the end of the
host’s write sequence, the X76F640 initiates the internal
nonvolatile write cycle. In order to take advantage of the
typical 5ms write cycle, ACK polling can begin
immediately. This involves issuing the start condition
followed by the new command code of 8 bits (1st byte of
the protocol.) If the X76F640 is still busy with the
nonvolatile write operation, it will issue a “no-ACK” in
response. If the nonvolatile write operation has
completed, an “ACK” will be returned and the host can
then proceed with the rest of the protocol.
Data ACK Polling Sequence
WRITE SEQUENCE
COMPLETED
ENTER ACK POLLING
ISSUE START
ISSUE NEW
COMMAND
CODE
ACK
RETURNED?
YES
PROCEED
NO
7025 FM 08
After the password sequence, there is always a nonvola-
tile write cycle. This is done to discourage random
guesses of the password if the device is being tampered
with. In order to continue the transaction, the X76F640
requires the master to perform an ACK polling with the
specific code of F0h. As with regular Acknowledge polling
the user can either time out for 10ms, and then issue the
ACK polling once, or continuously loop as described in the
flow.
Password ACK Polling Sequence
PASSWORD LOAD
COMPLETED
ENTER ACK POLLING
ISSUE START
ISSUE
PASSWORD
ACK COMMAND
ACK
RETURNED?
NO
YES
PROCEED
7025 FM 09
If the password that was inserted was correct, then an
“ACK” will be returned once the nonvolatile cycle is over,
in response to the ACK polling cycle immediately following
it.
If the password that was inserted was incorrect, then a “no
ACK” will be returned even if the nonvolatile cycle is over.
Therefore, the user cannot be certain that the password is
incorrect until the 10ms write cycle time has elapsed.
6

6 Page









X76F640W-2.7 pdf, datenblatt
X76F640
RESET AC SPECIFICATIONS
Power Up Timing
Symbol
Parameter
Min.
Typ(2)
Max.
Units
tPUR(1)
Time from Power Up to Read
1 mS
tPUW(1)
Time from Power Up to Write
5 mS
7025 FM T11
Notes: 1. Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled
and not 100% tested.
2. Typical values are for TA = 25˚C and VCC = 5.0V
Nonvolatile Write Cycle Timing
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
tWC(1)
Write Cycle Time
5 10 mS
7025 FM T12
Notes: 1. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
TIMING DIAGRAMS
Bus Timing
tR
tF
tHIGH
tLOW
SCL
tSU:STA
SDA IN
SDA OUT
tHD:STA
tSU:DAT
tHD:DAT
tAA tDH
tSU:STO
tBUF
7025 FM 18
Write Cycle Timing
SCL
SDA
8th bit of last byte
ACK
Stop
Condition
tWC
Start
Condition
7025 FM 19
12

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