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X76F041P Schematic ( PDF Datasheet ) - Xicor

Teilenummer X76F041P
Beschreibung PASS TM SecureFlash
Hersteller Xicor
Logo Xicor Logo 




Gesamt 21 Seiten
X76F041P Datasheet, Funktion
APPLICATION NOTE
A V A I LABLE
AN83 • Development Tools XK76C
Password Access Security Supervisor
4K
X76F041
4 x 128 x 8 Bit
PASSTM SecureFlash
FEATURES
• 64-Bit Password Security
• Three Password Modes
—Secure Read Access
—Secure Write Access
—Secure Configuration Access
• Programmable Configuration
—Read, Write and Configuration Access
Passwords
—Multiple Array Access/Functionality
—Retry Register/Counter
• 8 Byte Sector Write
• (4) 1K Memory Arrays
• ISO Response to Reset
• Low Power CMOS
—50µA Standby Current
—3mA Active Current
• 1.8V to 3.6V or 5V “Univolt” Read and Program
Power Supply Versions
• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
—ESD Protection: 2000V on All Pins
DESCRIPTION
The X76F041 is a password access security supervisor
device, containing four 128 x 8 bit SecureFlash arrays.
Access can be controlled by three 64-bit programmable
passwords, one for read operations, one for write opera-
tions and one for device configuration.
The X76F041 features a serial interface and software
protocol allowing operation on a simple two wire bus. The
bus signals are a clock input (SCL) and a bidirectional
data input and output (SDA). Access to the device is con-
trolled through a chip select input (CS), allowing any
number of devices to share the same bus.
The X76F041 also features a synchronous response to
reset; providing an automatic output of a pre-configured
32-bit data stream conforming to the ISO standard for
memory cards.
The X76F041 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
per sector and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
CS
SCL
SDA
RETRY
COUNTER
INTERFACE
LOGIC
RST
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7002-2.2 4/30/97 T3/C0/D0 SH
CHIP
ENABLE
DATA
TRANSFER
ARRAY ACCESS
ENABLE
PASSWORD ARRAY AND
PASSWORD VERIFICATION
LOGIC
ISO RESET RESPONSE
DATA REGISTER
CONFIGURATION
REGISTER
1
000–07F
080–0FF
100–17F
180–1FF
(4) 16 x 64
SECUREFLASH
ARRAYS
7002 ILL F01
Characteristics subject to change without notice






X76F041P Datasheet, Funktion
X76F041
Stop Condition
All communications must be terminated by a stop condi-
tion, which is a LOW to HIGH transition of SDA when
SCL is HIGH. A stop condition can only be issued after
the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data.
OPERATIONAL MODES
THE FIRST BYTE
IN THE PROTOCOL
0 0 0XXXXA
0 0 1XXXXA
0 1 0XXXXA
0 1 1XXXXA
1 0 0XXXXX
1 0 0XXXXX
1 0 0XXXXX
1 0 0XXXXX
1 0 0XXXXX
1 0 0XXXXX
1 0 0XXXXX
1 0 0XXXXX
1 0 0XXXXX
All the rest
THE SECOND BYTE
IN THE PROTOCOL
Write address
Read address
Write address
Read address
00000000
00010000
00100000
00110000
01000000
01010000
01100000
01110000
10000000
COMMAND DESCRIPTION
Write (Sector)
Read (Random / Sequential)
Write (Sector)
Read (Random / Sequential)
Program write-password
Program read-password
Program configuration-password
Reset write password (all 0’s)
Reset read password (all 0’s)
Program configuration registers
Read configuration registers
Mass program
Mass erase
Reserved
PASSWORD USED:
Write
Read
Configuration
Configuration
Write
Read
Configuration
Configuration
Configuration
Configuration
Configuration
Configuration
Configuration
7002 FRM T04
6

6 Page









X76F041P pdf, datenblatt
X76F041
Configuration of Passwords
The sequence in figure 14 will change (program) the
write, read and configuration passwords. The program-
ming of passwords is done twice prior to the nonvolatile
write cycle in order to verify that the new password is
consistent. After the eight bytes are entered in the sec-
ond pass, a comparison takes place. A mismatch will
cause the part to reset and enter into the standby mode
and a “no ACK” will be issued.
There is no way to read the Read/Write/Configuration
passwords.
Program Configuration Registers
This mode allows programming of the five configuration/
control registers using the configuration password. The
retry counter must be programmed with a value less than
the retry register. If it is programmed with a value larger
than the retry register there will be a wrap around.
Read Configuration Registers
This mode allows reading of the 5 configuration/control
registers with the configuration password. It may be use-
ful for monitoring purposes.
Figure 13. Configuration Random Read
SDA LINE
IF PASSWORD
MATCH THEN
FIRST BYTE
S BLOCK ADDRESS
T
A
R
T
C
M
D
A
X
A
X
A
X
A
X
A
8
AAAAAAAA
76543210
CONFIGURATION
PASSWORD 7
S
A AA
C CC
K KK
CONFIGURATION
PASSWORD 0
WAIT
tWC/ACK POLLING
AA
CC
KK
SECURE
READ SETUP
S
T
A
R A A A AAA A A
T 7 6 5 432 1 0
XXXXXXXXS
AA
CC
KK
DATA 0
S
T
A
RAAAAAAAA
T76543210
S
A
C
K
DATA 1
S
T
O
P
S
7002 ILL F16.3
Figure 14. Program Passwords
SDA LINE
IF PASSWORD
MATCH THEN
S
T
A
R
T
C
M
D
A
X
A
X
A
X
A
X
A
8
READ/WRITE/
CONFIGURATION
INSTRUCTION
OLD
PASSWORD 7
S
A
C
K
NEW
PASSWORD 7
AA
CC
KK
NEW
PASSWORD 0
OLD
PASSWORD 0
A
C
K
NEW
PASSWORD 7
WAIT
tWC/ACK POLLING
NEW
PASSWORD 0
S
T
O
P WAIT
S tWC
AAAA
CCCC
KKKK
AA
CC
KK
7002 ILL F17.1
12

12 Page





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