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X40626S14 Schematic ( PDF Datasheet ) - Xicor

Teilenummer X40626S14
Beschreibung Dual Voltage CPU Supervisor with 64K Serial EEPROM
Hersteller Xicor
Logo Xicor Logo 




Gesamt 23 Seiten
X40626S14 Datasheet, Funktion
Preliminary Information
64K
X40626
8K x 8 Bit
Dual Voltage CPU Supervisor with 64K Serial EEPROM
FEATURES
• Dual voltage monitoring
—V2Mon operates independent of VCC
• Watchdog timer with selectable timeout intervals
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
—User programmable VTRIP threshold
—Reset signal valid to VCC=1V
• Low power CMOS
—20µA max standby current, watchdog on
—1µA standby current, watchdog OFF
• 64Kbits of EEPROM
—64 byte page size
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lockprotection
• 400kHz 2-wire interface
—Slave addressing supports up to 4 devices on
the same bus
• 2.7V to 5.5V power supply operation
• Available Packages
—14-lead SOIC
—14-lead TSSOP
DESCRIPTION
The X40626 combines four popular functions, Power-on
Reset Control, Watchdog Timer, Dual Supply Voltage
Supervision, and Serial EEPROM Memory in one pack-
age. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to stabi-
lize before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontrol-
ler fails to restart a timer within a selectable time-out
interval, the device activates the RESET signal. The user
selects the interval from three preset values. Once
selected, the interval does not change, even after cycling
the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the set minimum VCC trip
point. RESET is asserted until VCC returns to proper
BLOCK DIAGRAM
V2MON
WP
SDA
SCL
S0
S1
V2 Monitor
Logic
+
VTRIP2
-
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Protect Logic
Status
Register
64KB
EEPROM
Array
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
V2FAIL
RESET
Power on and
Low Voltage
VCC
+ Reset
VTRIP
-
Generation
REV 1.1.15 2/11/04
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Characteristics subject to change without notice. 1 of 23






X40626S14 Datasheet, Funktion
X40626
Control Register
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is removed.
The Control Register is accessed at address FFFFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Register" below.
The user must issue a stop after sending this byte to
the register to initiate the nonvolatile cycle that stores
WD1, WD0, BP2, BP1, and BP0. The X40626 will not
acknowledge any data bytes written after the first byte
is entered.
The state of the Control Register can be read at any
time by performing a random read at address FFFFh.
Only one byte is read by each register read operation.
The X40626 resets itself after the first byte is read. The
master should supply a stop condition to be consistent
with the bus protocol, but a stop is not required to end
this operation.
7 6 5 43 2 10
WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and zeroes
to the other bits of the control register. Once set, WEL
remains set until either it is reset to 0 (by writing a “0” to
the WEL bit and zeroes to the other bits of the control
register) or until the part powers up again. Writes to the
WEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition.
BP2, BP1, BP0: Block Protect Bits - (Nonvolatile)
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block pro-
tect bits will prevent write operations to one of eight
segments of the array.
Protected Addresses
(Size)
Array Lock
0 0 0 None (factory setting)
None
0 0 1 1800h - 1FFFH (2K bytes) Upper 1/4 (Q4)
0 1 0 1000h - 1FFFH (4K bytes) Upper 1/2 (Q3,Q4)
0 1 1 0000h - 1FFFH (8K bytes) Full Array (All)
1 0 0 000h - 03FH (64 bytes) First Page (P1)
1 0 1 000h - 07FH (128 bytes) First 2 pgs (P2)
1 1 0 000h - 0FFH (256 bytes) First 4 pgs (P4)
1 1 1 000h - 1FFH (512 bytes) First 8 Pgs (P8)
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
WD1
0
0
1
1
WD0
0
1
0
1
Typ. Watchdog Time-out Period
1.4 Seconds
600 milliseconds
200 milliseconds
Disabled (factory setting)
Write Protect Enable
These devices have an advanced Block Lock scheme
that protects one of eight blocks of the array when
enabled. It provides hardware write protection through
the use of a WP pin and a nonvolatile Write Protect
Enable (WPEN) bit. Four of the 8 protected blocks
match the original Block Lock segments and this pro-
tection scheme is fully compatible with the current
devices using 2 bits of block lock control (assuming the
BP2 bit is set to 0).
The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Control Register control the
programmable Hardware Write Protect feature. Hard-
ware Write Protection is enabled when the WP pin and
the WPEN bit are HIGH and disabled when either the
WP pin or the WPEN bit is LOW. When the chip is Hard-
ware Write Protected, nonvolatile writes as well as to the
block protected sections in the memory array cannot be
written. Only the sections of the memory array that are
REV 1.1.15 2/11/04
www.xicor.com
Characteristics subject to change without notice. 6 of 23

6 Page









X40626S14 pdf, datenblatt
X40626
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues
the Word Address Bytes. After acknowledging receipts
of the Word Address Bytes, the master immediately
issues another start condition and the Slave Address
Byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 13 for the address,
acknowledge, and data transfer sequence.
Figure 13. Random Address Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
T
A
R
Slave
Address
T
Word Address
Byte 1
S 1 0 1 0 0 S1S0 0
A
C
K
Word Address
Byte 0
A
C
K
S
T
A
R
Slave
Address
T
S 1 0 1 0 0 S1S0 1
AA
CC
KK
Data
S
T
O
P
P
There is a similar operation, called “Set Current
Address” where the device does no operation, but
enters a new address into the address counter if a stop
is issued instead of the second start shown in Figure
13. The device goes into standby mode after the stop
and all bus activity will be ignored until a start is
detected. The next Current Address Read operation
reads from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indi-
cating it requires additional data. The device continues
to output data for each acknowledge received. The
master terminates the read operation by not respond-
ing with an acknowledge and then issuing a stop condi-
tion.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments
through all page and column addresses, allowing the
entire memory contents to be serially read during one
operation. At the end of the address space the counter
“rolls over” to address 0000H and the device continues
to output data for each acknowledge received. Refer to
Figure 14 for the acknowledge and data transfer
sequence.
REV 1.1.15 2/11/04
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Characteristics subject to change without notice. 12 of 23

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