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X4003 Schematic ( PDF Datasheet ) - Xicor

Teilenummer X4003
Beschreibung CPU Supervisor
Hersteller Xicor
Logo Xicor Logo 




Gesamt 18 Seiten
X4003 Datasheet, Funktion
X4003/X4005
CPU Supervisor
FEATURES
• Selectable watchdog timer
—Select 200ms, 600ms, 1.4s, off
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
nominal 4.62V, 4.38V, 2.92V, 2.68V, 1.75V
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—12µA typical standby current, watchdog on
—800nA typical standby current watchdog off
—3mA active current
• 400kHz I2C interface
• 1.8V to 5.5V power supply operation
• Available packages
—8-lead SOIC
—8-lead MSOP
BLOCK DIAGRAM
DESCRIPTION
These devices combine three popular functions, Power-
on Reset Control, Watchdog Timer, and Supply Voltage
Supervision. This combination lowers system cost,
reduces board space requirements, and increases
reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent
protection mechanism for microcontrollers. When the
microcontroller fails to restart a timer within a select-
able time out interval, the device activates the RESET/
RESET signal. The user selects the interval from three
preset values. Once selected, the interval does not
change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the minimum VCC trip
point. RESET/RESET is asserted until VCC returns to
proper operating level and stabilizes. Five industry stan-
dard VTRIP thresholds are available; however, Xicor’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements, or to fine-tune the thresh-
old for applications requiring higher precision.
WP
SDA
SCL
VCC
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Control
Register
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power on and
Low Voltage
Reset
Generation
RESET (X4003)
RESET (X4005)
REV 1.1.3 4/30/02
www.xicor.com
Characteristics subject to change without notice. 1 of 18






X4003 Datasheet, Funktion
X4003/X4005
The state of the control register can be read at any
time by performing a serial read operation. Only one
byte is read by each register read operation. The
X4003/X4005 resets itself after the first byte is read.
The master should supply a stop condition to be con-
sistent with the bus protocol, but a stop is not required
to end this operation.
76 5 4
0 WD1 WD0 0
3 2 10
0 RWEL WEL 0
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
control register.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the control register
during a write operation. This bit is a volatile latch that
powers up in the LOW (disabled) state. While the WEL
bit is LOW, writes the control register will be ignored
(no acknowledge will be issued after the data byte).
The WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register. Once
set, WEL remains set until either it is reset to 0 (by writ-
ing a “0” to the WEL bit and zeroes to the other bits of
the control register) or until the part powers up again.
Writes to the WEL bit do not cause a nonvolatile write
cycle, so the device is ready for the next operation
immediately after the stop condition.
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the watch-
dog timer. The options are shown below.
WD1
0
0
1
1
WD0
0
1
0
1
Watchdog Time Out Period
1.4 seconds
600 milliseconds
200 milliseconds
Disabled (factory setting)
Writing to the Control Register
Changing any of the nonvolatile bits of the control register
requires the following steps:
– Write a 02H to the control register to set the write
enable latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop.)
– Write a 06H to the control register to set both the
register write enable latch (RWEL) and the WEL bit.
This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop.)
– Write a value to the control register that has all the
control bits set to the desired state. This can be rep-
resented as 0xy0 0010 in binary, where xy are the
WD bits. (Operation preceeded by a start and ended
with a stop.) Since this is a nonvolatile write cycle it
will take up to 10ms to complete. The RWEL bit is
reset by this cycle and the sequence must be
repeated to change the nonvolatile bits again. If bit 2
is set to ‘1’ in this third step (0xy0 0110) then the
RWEL bit is set, but the WD1 and WD0 bits remain
unchanged. Writing a second byte to the control reg-
ister is not allowed. Doing so aborts the write opera-
tion and returns a NACK.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device consist-
ing of [02H, 06H, 02H] will reset all of the nonvolatile
bits in the control register to 0. A sequence of [02H,
06H, 06H] will leave the nonvolatile bits unchanged
and the RWEL bit remains set.
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data trans-
fers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family
operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 5.
REV 1.1.3 4/30/02
www.xicor.com
Characteristics subject to change without notice. 6 of 18

6 Page









X4003 pdf, datenblatt
X4003/X4005
TIMING DIAGRAMS
Bus Timing
tF tHIGH
SCL
SDA IN
tSU:STA
tHD:STA
tSU:DAT
tLOW
tHD:DAT
SDA OUT
tR
tA tDH
WP Pin Timing
SCL
SDA IN
WP
Start
Clk 1
Slave Address Byte
Clk 9
tSU:WP
tHD:WP
tSU:STO
tBUF
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
tWC
Stop
Condition
Start
Condition
Nonvolatile Write Cycle Timing
Symbol
tWC(7)
Parameter
Write cycle time
Min.
Typ.(1)
5
Max.
10
Unit
ms
Note: (7) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
REV 1.1.3 4/30/02
www.xicor.com
Characteristics subject to change without notice. 12 of 18

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