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X40010S8I-A Schematic ( PDF Datasheet ) - Xicor

Teilenummer X40010S8I-A
Beschreibung Dual Voltage Monitor with Integrated CPU Supervisor
Hersteller Xicor
Logo Xicor Logo 




Gesamt 25 Seiten
X40010S8I-A Datasheet, Funktion
New Features
• Monitor Voltages: 5V to 0.9V
• Independent Core Voltage Monitor
Preliminary Datasheet
X40010/X40011/X40014/X40015
Dual Voltage Monitor with Integrated CPU Supervisor
FEATURES
• Dual voltage detection and reset assertion
—Standard reset threshold settings
See Selection table on page 2.
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three voltages or detect power fail
• Independent Core Voltage Monitor (V2MON)
• Fault detection register
• Selectable power on reset timeout (0.05s,
0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval (25ms, 200ms,
1.4s, off)
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8-lead SOIC, TSSOP
APPLICATIONS
• Communication Equipment
—Routers, Hubs, Switches
—Disk Arrays, Network Storage
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
— Computers
—Network Servers
DESCRIPTION
The X40010/11/14/15 combines power-on reset con-
trol, watchdog timer, supply voltage supervision, and
secondary voltage supervision, in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to VCC activates the power on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator
to stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
VCC falls below the minimum VTRIP1 point. RESET/
RESET is active until VCC returns to proper operating
level and stabilizes. A second voltage monitor circuit
tracks the unregulated supply to provide a power fail
warning or monitors different power supply voltage.
Three common low voltage combinations are avail-
able, however, Xicor’s unique circuits allows the
BLOCK DIAGRAM
SDA
SCL
VCC
(V1MON)
V2MON
Data
Register
Command
Decode Test
& Control
Logic
Threshold
Reset Logic
Fault Detection
Register
Status
Register
Watchdog Timer
and
Reset Logic
User Programmable
VTRIP1
User Programmable
VTRIP2
+
-
V2MON
+ VCC
Power on,
Low Voltage
Reset
Generation
-
*X40010/11 = V2MON*
X40014/15 = VCC
WDO
RESET
X40010/14
RESET
X40011/15
V2FAIL
REV 1.3.4 7/12/02
www.xicor.com
Characteristics subject to change without notice. 1 of 25






X40010S8I-A Datasheet, Funktion
X40010/X40011/X40014/X40015 – Preliminary
Figure 5. VTRIPX Set/Reset Sequence (X = 1, 2)
VTRIPX Programming
No Desired
VTRIPX
Present Value
YES
Execute
VTRIPX Reset Sequence
New VX applied =
Old VX applied + | Error |
NO
Execute
Set Higher VTRIPX Sequence
Execute
Set Higher VX Sequence
Apply VCC and Voltage
> Desired VTRIPX to VX
Decrease VX
Vx = VCC, VxMON
Note: X = 1, 2
Let: MDE = Maximum Desired Error
MDE+
Desired Value
MDE
Acceptable
Error Range
Error = Actual - Desired
New VX applied =
Old VX applied - | Error |
Execute Reset VTRIPX
Sequence
Error < MDE
Output Switches?
YES
Actual VTRIPX -
Desired VTRIPX
Error > MDE+
| Error | < | MDE |
DONE
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and zeros
to the other bits of the control register.
Once set, WEL remains set until either it is reset to 0
(by writing a “0” to the WEL bit and zeros to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high volt-
age write cycle, so the device is ready for the next
operation immediately after the stop condition.
REV 1.3.4 7/12/02
www.xicor.com
Characteristics subject to change without notice. 6 of 25

6 Page









X40010S8I-A pdf, datenblatt
X40010/X40011/X40014/X40015 – Preliminary
SERIAL DEVICE ADDRESSING
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FFhex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FFhex
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always ‘101x’. Where
x=0 is for Array, x=1 is for Control Register or Fault
Detection Register.
– next two bits are ‘0’.
– next bit that becomes the MSB of the address.
Figure 11. X40010/11/14/15 Addressing
Slave Byte
Control Register
1 0 1 1 0 0 1 R/W
Fault Detection Register 1 0 1 1 0 0 0 R/W
Word Address
Control Register
111 11111
Fault Detection Register 1 1 1 1 1 1 1 1
Figure 12. Current Address Read Sequence
.
S
Signals from
the Master
t
a
r
Slave
Address
t
SDA Bus
10 1000
1
S
t
o
p
Signals from
the Slave
Data
Figure 13. Random Address Read Sequence
Signals from
the Master
SDA Bus
S
t Slave
a Address
r
t
101 00 0
Byte
Address
S
t Slave
a Address
r
t
1
Signals from
the Slave
AA
CC
KK
A
C
K
Data
S
t
o
p
REV 1.3.4 7/12/02
www.xicor.com
Characteristics subject to change without notice. 12 of 25

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