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PDF X3101 Data sheet ( Hoja de datos )
| Número de pieza | X3101 | |
| Descripción | 3 or 4 Cell Li-Ion Battery Protection and Monitor IC | |
| Fabricantes | Xicor | |
| Logotipo |  |
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APPLICATION NOTE
A V A I LABLE
3 or 4 Cell Li-Ion BATTERY PACKS
PPrreelliimmiinnaarryy Information
X3100/X3101
4 cell / 3 cell
3 or 4 Cell Li-Ion Battery Protection and Monitor IC
FEATURE
• Software Selectable Protection Levels and
Variable Protect Detection/Release Times
• Integrated FET Drive Circuitry
• Cell Voltage and Current Monitoring
• 0.5% Accurate Voltage Regulator
• Integrated 4kbit EEPROM
• Flexible Power Management with 1µA Sleep
Mode
• Cell Balancing Control
BENEFIT
• Optimize protection for chosen cells to allow
maximum use of pack capacity.
• Reduce component count and cost
• Simplify implementation of gas gauge
• Accurate voltage and current measurements
• Record battery history to optimize gas gauge,
track pack failures and monitor system use
• Reduce power to extend battery life
• Increase battery capacity and improve cycle life
battery life
DESCRIPTION
The X3100 is a protection and monitor IC for use in
battery packs consisting of 4 series Lithium-Ion
battery cells. The X3101 is designed to work in 3 cell
applications. Both devices provide internal over-
charge, over-discharge, and over-current protection
circuitry, internal EEPROM memory, an internal
voltage regulator, and internal drive circuitry for
external FET devices that control cell charge,
discharge, and cell voltage balancing.
Over-charge, over-discharge, and over-current
thresholds reside in an internal EEPROM memory
register and are selected independently via software
using a 3MHz SPI serial interface. Detection and time-
out delays can also be individually varied using
external capacitors.
Using an internal analog multiplexer, the X3100 or
X3101 allow battery parameters such as cell voltage
and current (using a sense resistor) to be monitored
externally by a separate microcontroller with A/D
converter. Software on this microcontroller implements
gas gauge and cell balancing functionality in software.
The X3100 and X3101 contain a current sense
amplifier. Selectable gains of 10, 25, 80 and 160 allow
an external 10 bit A/D converter to achieve better
resolution than a more expensive 14 bit converter.
An internal 4kbit EEPROM memory featuring
IDLock™, allows the designer to partition and “lock in”
written battery cell/pack data.
The X3100 and X3101 are each housed in a 28 Pin
TSSOP package.
FUNCTIONAL DIAGRAM
VCC RGP RGC RGO
UVP/OCP OVP/LMON
VCELL1
CB1
VCELL2
CB2
VCELL3
CB3
VCELL4/VSS
CB4
Over-charge
Over-discharge
Protection
Sense
Circuits
Protection
Sample Rate
Timer
Over-current
Protection &
Current Sense
5VDC
Regulator
FET Control
Circuitry
Internal Voltage Regulator
Power On reset &
Status Register
Protection Circuit
Timing Control
& Configuration
Configuration
Register
4 kbit
EEPROM
Control
Register
Analog
MUX
SPI
I/F
AS0
AS1
AS2
AO
S0
SCK
CS
SI
VSS
VCS1 VCS2 OVT UVT OCT
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice. 1 of 40
1 page  
X3100/X3101 – Preliminary Information
Figure 1. Typical Application Circuit
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice. 5 of 40
5 Page 
X3100/X3101 – Preliminary Information
Current Sense Gain (CSG1, CSG0)
These bits set the gain of the current sense amplifier.
These are x10, x25, x80 and x160. For more detail, see
section “Current Monitor Function” on page 20.
Table 14. Current Sense Gain Control
Control Register Bits
CSG1
CSG0
Operation
0 0 Set current sense gain=x10
0 1 Set current sense gain=x25
1 0 Set current sense gain=x80
1 1 Set current sense gain=x160
Charge/Discharge Control (OVPC, UVPC)
The OVPC and UVPC bits allow control of cell charge
and discharge externally, via the SPI port. These bits
control the OVP/LMON and UVP/OCP pins, which in turn
control the external power FETs.
Using P-channel power FETs ensures that the FET is
on when the pin voltage is low (Vss), and off when the
pin voltage is high (Vcc).
OVP/LMON and UVP/OCP can be controlled by using
the WCNTR Instruction to set bits OVPC and UVPC in
the Control register (See page 10).
Table 15. UVP/OVP Control
Control Register Bits
OVPC
UVPC
1x
0x
x1
x0
Operation
Pin OVP=VSS (FET ON)
Pin OVP=VCC (FET OFF)
Pin UVP=VSS (FET ON)
Pin UVP=VCC (FET OFF)
It is possible to set/change the values of OVPC and
UVPC during a protection mode. A change in the state
of the pins OVP/LMON and UVP/OCP, however, will not
take place until the device has returned from the
protection mode.
Cell Voltage Balance Control (CBC1-CBC4)
This function can be used to adjust individual battery
cell voltage during charging. Pins CB1–CB4 are used to
control external power switching devices. Cell voltage
balancing is achieved via the SPI port.
Table 16. CB1—CB4 Control
Control Register Bits
CBC4 CBC3 CBC2 CBC1
Operation
x x x 1 Set CB1=VCC (ON)
x x x 0 Set CB1=VSS (OFF)
x x 1 x Set CB2=VCC (ON)
x x 0 x Set CB2=VSS (OFF)
x 1 x x Set CB3=VCC (ON)
x 0 x x Set CB3=VSS (OFF)
1 x x x Set CB4=VCC (ON)
0 x x x Set CB4=VSS (OFF)
CB1–CB4 can be controlled by using the WCNTR In-
struction to set bits CBC1–CBC4 in the control register
(Table 16).
STATUS REGISTER
The status of the X3100 or X3101 can be verified by
using the RDSTAT command to read the contents of the
Status Register (Table 17).
Table 17. Status Register.
76543
2
00000
CCES+
OVDS
1
UVDS
0
VRGS+
OCDS
The function of each bit in the status register is shown
in Table 18.
Bit 0 of the status register (VRGS+OCDS) actually
indicates the status of two conditions of the X3100 or
X3101. Voltage Regulator Status (VRGS) is an
internally generated signal which indicates that the
output of the Voltage Regulator (VRGO) has reached an
output of 5VDC ± 0.5%. In this case, the voltage
regulator is said to be “tuned”. Before the signal VRGS
goes low (i.e. before the voltage regulator is tuned), the
voltage at the output of the regulator is nominally 5VDC
± 10% (See section “Voltage Regulator” on page 21.)
Over-current Detection Status (OCDS) is another
internally generated signal which indicates whether or
not the X3100 or X3101 is in over-current protection
mode.
Signals VRGS and OCDS are logically OR’ed together
(VRGS+OCDS) and written to bit 0 of the status register
(See Table 18, Table 17 and Figure 2).
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice. 11 of 40
11 Page | ||
| Páginas | Total 40 Páginas | |
| PDF Descargar | [ Datasheet X3101.PDF ] | |
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