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X20C16DMB-45 Schematic ( PDF Datasheet ) - Xicor

Teilenummer X20C16DMB-45
Beschreibung High Speed AUTOSTORE NOVRAM
Hersteller Xicor
Logo Xicor Logo 




Gesamt 21 Seiten
X20C16DMB-45 Datasheet, Funktion
APPLICATION NOTE
AVA I L A B L E
X20C16 AN56
16K X20C16
High Speed AUTOSTORE™ NOVRAM
2K x 8 Bit
FEATURES
Fast Access Time: 35ns, 45ns, 55ns
High Reliability
—Endurance: 1,000,000 Nonvolatile Store
Operations
—Retention: 100 Years Minimum
AUTOSTORE™ NOVRAM
—Automatically Stores RAM Data Into the
E2PROM Array When VCC Low Threshold is
Detected
—User Enabled Option
—Open Drain AUTOSTORE Status Output Pin
Power-on Recall
—E2PROM Data Automatically Recalled Into
RAM Upon Power-up
Software Data Protection
—Locks Out Inadvertent Store Operations
Low Power CMOS
—Standby: 250µA
Infinite E2PROM Array Recall, and RAM Read
and Write Cycles
PIN CONFIGURATION
PLASTIC
CERDIP
NE
NC
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 28 VCC
2 27 WE
3 26 AS
4 25 A8
5 24 A9
6 23 NC
7 22
8 X20C16 21
9 20
10 19
11 18
12 17
13 16
14 15
OE
A10
CE
NC
OE
I/O7
I/O6
A9
A8
AS
I/O5 WE
I/O4
I/O3
VCC
NE
3826 FHD F02
NC
3826 FHD F15.1
A7
A6
A5
A4
A3
SOIC
1 28
2 27
3 26
4 25
5 24
6 23
7 22
X20C16
8 21
9 20
10 19
11 18
12 17
13 16
14 15
AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
©Xicor, Inc. 1991, 1995, 1996 Patents Pending
3826-2.9 7/31/97 T4/C0/D0 SH
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
DESCRIPTION
The Xicor X20C16 is a 2K x 8 NOVRAM featuring a high-
speed static RAM overlaid bit-for-bit with a nonvolatile
electrically erasable PROM (E2PROM) and the
AUTOSTORE feature which automatically saves the
RAM contents to E2PROM at power-down. The X20C16
is fabricated with advanced CMOS floating gate technol-
ogy to achieve high speed with low power and wide
power-supply margin. The X20C16 features a compat-
ible JEDEC approved pinout for byte-wide memories,
for industry standard RAMs, ROMs, EPROMs, and
E2PROMs.
The NOVRAM design allows data to be easily trans-
ferred from RAM to E2PROM (store) and E2PROM to
RAM (recall). The store operation is completed in 5ms or
less and the recall operation is completed in 10µs or
less. An automatic array recall operation reloads the
contents of the E2PROM into RAM upon power-up.
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
E2PROM, and a minimum 1,000,000 store operations to
the E2PROM. Data retention is specified to be greater
than 100 years.
TSOP
LCC
PLCC
X20C16
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 NC
A3 8
A2 9
A1 10
X20C16
(TOP VIEW)
26 NC
25 OE
24 A10
A0 11
23 CE
3826 ILL F17.2
NC
I/O0
12 22
13 21
14 15 16 17 18 19 20
I/O7
I/O6
3826 FHD F03
Characteristics subject to change without notice
1






X20C16DMB-45 Datasheet, Funktion
X20C16
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)
Read Cycle Limits
Symbol
Parameter
X20C16-35
–40 to +85°C
Min. Max.
X20C16-45
Min. Max.
X20C16-55
Min. Max. Units
tRC Read Cycle Time
35 45
55 ns
tCE Chip Enable Access Time
35 45 55 ns
tAA Address Access Time
35 45 55 ns
tOE Output Enable Access Time
20 25 30 ns
tLZ(3)
Chip Enable to Output in Low Z
0
0
0 ns
tOLZ(3)
Output Enable to Output in Low Z
0
0
0 ns
tHZ(3)
Chip Disable to Output in High Z
0 15 0
20 0
25 ns
tOHZ(3) Output Disable to Output in High Z
0 15 0
20 0
25 ns
tOH
Output Hold From Address Change
0
0
0 ns
3826 PGM T10
Read Cycle
ADDRESS
CE
OE
WE
DATA I/O
tRC
tCE
tOE
tOLZ
tLZ
DATA VALID
tOH
tAA
tHZ
DATA VALID
tOHZ
3826 FHD F05
Note: (3) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with
CL = 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the outptus are no longer driven.
6

6 Page









X20C16DMB-45 pdf, datenblatt
X20C16
AUTOSTORE Feature
The AUTOSTORE feature automatically saves the con-
tents of the X20C16’s static RAM to the on-board bit-for-
bit shadow E2PROM at power-down. This circuitry in-
sures that no data is lost during accidental power-downs
or general system crashes, and is ideal for microproces-
sor caching systems, embedded software systems, and
general system back-up memory.
AUTOSTORE CYCLE Timing Diagrams
The AUTOSTORE instruction (EAS) to the SDP register
sets the AUTOSTORE enable latch, allowing the X20C16
to automatically perform a store operation whenever
VCC falls below the AUTOSTORE threshold (VASTH).
VCC must remain above the AUTOSTORE Cycle End
Voltage (VASEND) for the duration of the store cycle
(tASTO). The detailed timing for this feature is illustrated
in the AUTOSTORE timing diagram, below. Once the
AUTOSTORE cycle is initiated, all other device func-
tions are inhibited.
5 VCC
4 AUTOSTORE CYCLE IN PROGRESS VASTH
VASEND
3
2 tASTO
1 STORE TIME
TIME (ms)
VASTH
0V
AS
VCC
tPUR
tASTO
tPUR
AUTOSTORE CYCLE LIMITS
Symbol
tASTO
VASTH
VASEND
Parameter
AUTOSTORE Cycle Time
AUTOSTORE Threshold Voltage
AUTOSTORE Cycle End Voltage
Min.
4.0
3.5
X20C16
Max.
2.5
4.3
3826 FHD F14
Units
ms
V
V
3826 PGM T15
12

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