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X20C05P-55 Schematic ( PDF Datasheet ) - Xicor

Teilenummer X20C05P-55
Beschreibung High Speed AUTOSTORE NOVRAM
Hersteller Xicor
Logo Xicor Logo 




Gesamt 19 Seiten
X20C05P-55 Datasheet, Funktion
APPLICATION NOTE
AVA I L A B L E
X20C05 AN56
4K X20C05
High Speed AUTOSTORE™ NOVRAM
512 x 8
FEATURES
Fast Access Time: 35ns, 45ns, 55ns
High Reliability
—Endurance: 1,000,000 Nonvolatile Store
Operations
—Retention: 100 Years Minimum
Power-on Recall
—E2PROM Data Automatically Recalled Into
SRAM Upon Power-up
AUTOSTORE™ NOVRAM
—User Enabled Option
—Automatically Stores SRAM Data Into the
E2PROM Array When VCC Low Threshold is
Detected
—Open Drain AUTOSTORE Status Output Pin
Software Data Protection
—Locks Out Inadvertent Store Operations
Low Power CMOS
—Standby: 250µA
Infinite E2PROM Array Recall, and RAM Read
and Write Cycles
Upward compatible with X20C16 (16K)
DESCRIPTION
The Xicor X20C05 is a 512 x 8 NOVRAM featuring a
high-speed static RAM overlaid bit-for-bit with a non-
volatile electrically erasable PROM (E2PROM). The
X20C05 is fabricated with advanced CMOS floating
gate technology to achieve high speed with low power
and wide power-supply margin. The X20C05 features
the JEDEC approved pinout for byte-wide memories,
compatible with industry standard RAMs, ROMs,
EPROMs, and E2PROMs.
The NOVRAM design allows data to be easily trans-
ferred from RAM to E2PROM (store) and E2PROM to
RAM (recall). The store operation is completed in 5ms or
less and the recall operation is completed in 5µs or less.
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
E2PROM, and a minimum 1,000,000 store operations to
the E2PROM. Data retention is specified to be greater
than 100 years.
PIN CONFIGURATION
PLASTIC
CERDIP
NE
NC
7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 X20C05 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
AS
A8
NC
NC
OE
NC
CE
I/O7
I/O6
I/O5
I/O4
I/O3
3827 FHD F02
AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
©Xicor, Inc. 1991 - 1997 Patents Pending
3827-2.7 7/31/97 T4/C0/D0 SH
LCC
PLCC
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 NC
A4 7
27 NC
A3 8
A2 9
A1 10
X20C05
(TOP VIEW)
26 NC
25 OE
24 NC
A0 11
23 CE
NC 12
22 I/O7
I/O0 13
21 I/O6
14 15 16 17 18 19 20
3827 FHD F03
1 Characteristics subject to change without notice






X20C05P-55 Datasheet, Funktion
X20C05
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)
Read Cycle Limits
Symbol
Parameter
X20C05-35
Min. Max.
X20C05-45
Min. Max.
X20C05-55
Min. Max. Units
tRC Read Cycle Time
35 45
55 ns
tCE Chip Enable Access Time
35 45 55 ns
tAA Address Access Time
35 45 55 ns
tOE Output Enable Access Time
20 25 30 ns
tLZ(3)
Chip Enable to Output in Low Z
0
0
0 ns
tOLZ(3)
Output Enable to Output in Low Z
0
0
0 ns
tHZ(3)
Chip Disable to Output in High Z
15 20
25 ns
tOHZ(3) Output Disable to Output in High Z 15 20
25 ns
tOH
Output Hold From Address Change
0
0
0 ns
3827 PGM T10
Read Cycle
ADDRESS
CE
OE
VIH
WE
DATA I/O
tRC
tCE
tOE
tOLZ
tLZ
DATA VALID
tOH
tAA
tHZ
DATA VALID
tOHZ
3827 FHD F05
Note: (3) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ and tOHZ are measured, with CL = 5pF,
from the point when CE or OE return HIGH (whichever occurs first) to the time when the outptus are no longer driven.
6

6 Page









X20C05P-55 pdf, datenblatt
X20C05
AUTOSTORE Feature
The AUTOSTORE feature automatically saves the con-
tents of the X20C05’s RAM to the on-board bit-for-bit
shadow E2PROM at power-down. This circuitry insures
that no data is lost during accidental power-downs or
general system crashes, and is ideal for microprocessor
caching systems, embedded software systems, and
general system back-up memory.
The AUTOSTORE instruction (EAS) to the SDP register
sets the AUTOSTORE enable latch, allowing the X20C05
AUTOSTORE CYCLE Timing Diagrams
to automatically perform a store operation whenever VCC
falls below the AUTOSTORE threshold (VASTH). VCC
must remain above the AUTOSTORE Cycle End Volt-
age (VASEND) for the duration of the store cycle (tASTO).
The detailed timing for this feature is illustrated in the
AUTOSTORE timing diagram, below. Once the
AUTOSTORE cycle is initiated, all other device functions
are inhibited.
5 VCC
4 AUTOSTORE CYCLE IN PROGRESS VASTH
VASEND
3
2 tASTO
1 STORE TIME
TIME (ms)
VASTH
0V
AS
VCC
tPUR tASTO
tPUR
3827 FHD F14
AUTOSTORE CYCLE LIMITS
Symbol
tASTO
VASTH
VASEND
Parameter
AUTOSTORE Cycle Time
AUTOSTORE Threshold Voltage
AUTOSTORE Cycle End Voltage
Min.
4.0
3.5
X20C05
Max.
2.5
4.3
Units
ms
V
V
3827 PGM T15
12

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