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PDF XC3000FM Data sheet ( Hoja de datos )
| Número de pieza | XC3000FM | |
| Descripción | Logic Cell Array Families | |
| Fabricantes | Xilinx | |
| Logotipo |  |
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XC3000 Logic Cell Array Families
Table of Contents
Overview .............................................................. 2-104
XC3000, XC3000A, XC3000L, XC3100, XC3100A
Logic Cell Array Families ................................. 2-105
Architecture ...................................................... 2-106
Programmable Interconnect ............................. 2-111
Crystal Oscillator .............................................. 2-117
Programming ................................................... 2-118
Special Configuration Functions ...................... 2-122
Master Serial Mode .......................................... 2-124
Master Serial Mode Programming
Switching Characteristics ............................. 2-125
Master Parallel Mode ....................................... 2-126
Master Parallel Mode Programming
Switching Characteristics ............................. 2-127
Peripheral Mode ............................................... 2-128
Peripheral Mode Programming
Switching Characteristics ............................. 2-129
Slave Serial Mode ............................................ 2-130
Slave Serial Mode Programming
Switching Characteristics ............................. 2-131
Program Readback Switching
Characteristics ............................................. 2-131
General LCA Switching Characteristics ........... 2-132
Performance .................................................... 2-133
Power ............................................................... 2-134
Pin Descriptions ............................................... 2-136
Pin Functions During Configuration.................. 2-138
XC3000 Families Pin Assignments .................. 2-139
XC3000 Families Pinouts ................................. 2-140
Component Availability ..................................... 2-151
Ordering Information ........................................ 2-152
XC3000 Logic Cell Array Family ........................... 2-153
Absolute Maximum Ratings ............................. 2-154
Operating Conditions ....................................... 2-154
DC Characteristics ........................................... 2-155
Switching Characteristic Guidelines
CLB .............................................................. 2-156
Buffer ........................................................... 2-156
IOB .............................................................. 2-158
Ordering Information ........................................ 2-160
Component Availability ..................................... 2-160
XC3000A Logic Cell Array Familiy ....................... 2-161
Absolute Maximum Ratings ............................. 2-162
Operating Conditions ....................................... 2-162
DC Characteristics ........................................... 2-163
Switching Characteristic Guidelines
CLB .............................................................. 2-164
Buffer ........................................................... 2-164
IOB .............................................................. 2-166
Ordering Information ........................................ 2-168
Component Availability ..................................... 2-168
XC3000L Low Voltage Logic Cell Array Family .... 2-169
Absolute Maximum Ratings ............................. 2-170
Operating Conditions ....................................... 2-170
DC Characteristics ........................................... 2-171
Switching Characteristic Guidelines
CLB .............................................................. 2-172
Buffer ........................................................... 2-172
IOB .............................................................. 2-174
Ordering Information ........................................ 2-176
Component Availability ..................................... 2-176
XC3100, XC3100A Logic Cell Array Families ....... 2-177
Absolute Maximum Ratings ............................. 2-178
Operating Conditions ....................................... 2-178
DC Characteristics ........................................... 2-179
Switching Characteristic Guidelines
CLB .............................................................. 2-180
Buffer ........................................................... 2-180
IOB .............................................................. 2-182
Ordering Information ........................................ 2-184
Component Availability ..................................... 2-184
2-103
1 page  
Read or
Write
Data
Q
Configuration
Control
Q
X5382
The method of loading the configuration data is selectable.
Two methods use serial data, while three use byte-wide
data. The internal configuration logic utilizes framing
information, embedded in the program data by the XACT
development system, to direct memory-cell loading. The
serial-data framing and length-count preamble provide
programming compatibility for mixes of various LCA device
devices in a synchronous, serial, daisy-chain fashion.
Figure 2. Static Configuration Memory Cell.
It is loaded with one bit of configuration program and
controls one program selection in the Logic Cell Array.
The memory cell outputs Q and Q use ground and VCC
levels and provide continuous, direct control. The addi-
tional capacitive load together with the absence of address
decoding and sense amplifiers provide high stability to the
cell. Due to the structure of the configuration memory cells,
they are not affected by extreme power-supply excursions
or very high levels of alpha particle radiation. In reliability
testing, no soft errors have been observed even in the
presence of very high doses of alpha radiation.
I/O Block
Each user-configurable IOB shown in Figure 3, provides
an interface between the external package pin of the
device and the internal user logic. Each IOB includes both
registered and direct input paths. Each IOB provides a
programmable 3-state output buffer, which may be driven
by a registered or direct output signal. Configuration
options allow each IOB an inversion, a controlled slew rate
and a high impedance pull-up. Each input circuit also
provides input clamping diodes to provide electrostatic
protection, and circuits to inhibit latch-up produced by
input currents.
PROGRAM-CONTROLLED MEMORY CELLS
OUT
INVERT
3-STATE
INVERT
OUTPUT
SELECT
SLEW
RATE
PASSIVE
PULL UP
Vcc
3- STATE
(OUTPUT ENABLE)
OUT
T
O
DIRECT IN
REGISTERED IN
I
Q
DQ
FLIP
FLOP
R
QD
FLIP
FLOP
or
LATCH
R
OK IK
OUTPUT
BUFFER
I/O PAD
TTL or
CMOS
INPUT
THRESHOLD
(GLOBAL RESET)
CK1
PROGRAM
CONTROLLED
MULTIPLEXER
CK2
= PROGRAMMABLE INTERCONNECTION POINT or PIP
X3029
Figure 3. Input/Output Block.
Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice of two
clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable. A clock line that
triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice versa. Passive pull-up can
only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS thresholds.
2-107
5 Page 
Figure 9. LCA General-Purpose Interconnect.
Composed of a grid of metal segments that may be intercon-
nected through switch matrices to form networks for CLB and
IOB inputs and outputs.
X2664
Special buffers within the general interconnect areas pro-
vide periodic signal isolation and restoration for improved
performance of lengthy nets. The interconnect buffers are
available to propagate signals in either direction on a given
general interconnect segment. These bidirectional (bidi)
buffers are found adjacent to the switching matrices,
above and to the right and may be highlighted by the use
of the Show BIDI command in the XACT system. The other
PIPs adjacent to the matrices are accessed to or from
Longlines. The development system automatically de-
fines the buffer direction based on the location of the
interconnection network source. The delay calculator of
the XACT development system automatically calculates
and displays the block, interconnect and buffer delays for
any paths selected. Generation of the simulation netlist
with a worst-case delay model is provided by an XACT
option.
Direct Interconnect
Direct interconnect, shown in Figure 11, provides the most
efficient implementation of networks between adjacent
CLBs or I/O Blocks. Signals routed from block to block
using the direct interconnect exhibit minimum interconnect
propagation and use no general interconnect resources.
For each CLB, the X output may be connected directly to
the B input of the CLB immediately to its right and to the C
input of the CLB to its left. The Y output can use direct
interconnect to drive the D input of the block immediately
above and the A input of the block below. Direct intercon-
1 2 34 5
6 7 8 9 10
11 12 13 14 15
16 17 18 19 20
1105 13
Figure 10. Switch Matrix Interconnection Options for Each
Pin. Switch matrices on the edges are different. Use Show
Matrix menu option in the XACT system
X2663
Figure 11. CLB X and Y Outputs.
The X and Y outputs of each CLB have single contact, direct
access to inputs of adjacent CLBs
2-113
11 Page | ||
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| PDF Descargar | [ Datasheet XC3000FM.PDF ] | |
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