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XC1701LPD8I Schematic ( PDF Datasheet ) - Xilinx

Teilenummer XC1701LPD8I
Beschreibung Configuration PROMs
Hersteller Xilinx
Logo Xilinx Logo 




Gesamt 12 Seiten
XC1701LPD8I Datasheet, Funktion
0
R XC1700E and XC1700L Series
Configuration PROMs
DS027 (v3.1) July 5, 2000
08
Features
• One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA devices
• Simple interface to the FPGA; requires only one user
I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
• XC17128E/EL, XC17256E/EL, XC1701 and XC1700L
series support fast configuration
• Low-power CMOS Floating Gate process
• XC1700E series are available in 5V and 3.3V versions
• XC1700L series are available in 3.3V only
• Available in compact plastic packages: 8-pin SOIC,
8-pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC,
44-pin PLCC or 44-pin VQFP.
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages.
• Guaranteed 20 year life data retention
Product Specification
Description
The XC1700 family of configuration PROMs provides an
easy-to-use, cost-effective method for storing large Xilinx
FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to most commercial PROM programmers.
VCC VPP GND
RESET/
OE
or
OE/
RESET
CE
CLK
Address Counter
TC
CEO
EPROM
Cell
Matrix
Output
OE
DATA
DS027_01_021500
Figure 1: Simplified Block Diagram (does not show programming circuit)
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS027 (v3.1) July 5, 2000
Product Specification
www.xilinx.com
1-800-255-7778
1






XC1701LPD8I Datasheet, Funktion
XC1700E and XC1700L Series Configuration PROMs
R
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high impedance
state regardless of the state of the OE input.
Programming
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
Table 1: Truth Table for XC1700 Control Inputs
Control Inputs
Outputs
RESET
Inactive
CE
Low
Internal Address
If address < TC(1): increment
If address > TC(2): dont change
DATA
Active
High-Z
CEO
High
Low
ICC
Active
Reduced
Active
Low
Held reset
High-Z
High
Active
Inactive
High
Not changing
High-Z
High
Standby
Active
High
Held reset
High-Z
High
Standby
Notes:
1. The XC1700 RESET input has programmable polarity
2. TC = Terminal Count = highest address value. TC + 1 = address 0.
6
www.xilinx.com
DS027 (v3.1) July 5, 2000
1-800-255-7778
Product Specification

6 Page









XC1701LPD8I pdf, datenblatt
XC1700E and XC1700L Series Configuration PROMs
R
Marking Information
Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on
the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows:
1701L J C
Device Number
1736E
1765E
1765X(1)
17128E
17128X(1)
17256E
17256X(1)
1704L
1702L
1701
1701L
17512L
Package Type
P = 8-pin Plastic DIP
S(2) = 8-pin Plastic Small-Outline Package
V = 8-pin Plastic Small-Outline Thin Package
S(3) = 20-pin Plastic Small-Outline Package
J = 20-pin Plastic Leaded Chip Carrier
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
Operating Range/Processing
C = Commercial (TA = 0° to +70°C)
I = Industrial (TA = 40° to +85°C)
Notes:
1. When marking the device number on the EL parts, an X is used in place of an EL.
2. For XC1700E/EL only.
3. For XC1700L only.
Revision History
The following table shows the revision history for this document.
Date
7/14/98
9/8/98
12/18/98
1/27/99
7/8/99
3/30/00
07/05/00
Version
1.1
2.0
2.1
2.2
2.3
3.0
3.1
Revision
Major revisions to include the XC1704L, XC1702L, and the XQ1701L devices, packages and
operating conditions. Also revised the timing specifications on page 9.
Revised the marking information for the VQ44. Updated "DC Characteristics Over Operating
Condition" on page 7 and page 8. Added references to the XC4000XLA and XC4000XV
families in "Xilinx FPGAs and Compatible PROMs" on page 3 and Figure 2 on page 5.
Added Virtex FPGAs to "Xilinx FPGAs and Compatible PROMs" on page 3. Added the PC44
package for the XC1702L and XC1704L products.
Changed Military ICCS.
Changed ICCS standby on XC1702/XC1704 from 50 mA to 300 mA.
Combined data sheets XC1700E and XC1700L. Added DS027, removed Military Specs.
Added Virtex-E and EM references.
Added 4.7K resistor to Figure 2, updated format.
12
www.xilinx.com
DS027 (v3.1) July 5, 2000
1-800-255-7778
Product Specification

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