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PDF XC1701 Data sheet ( Hoja de datos )
| Número de pieza | XC1701 | |
| Descripción | Serial Configuration PROMs | |
| Fabricantes | Xilinx | |
| Logotipo |  |
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®
December 10, 1997 (Version 1.1)
0
XC1701L (3.3V), XC1701 (5.0V) and
XC17512L (3.3V)
Serial Configuration PROMs
0 5* Product Specification
Features
• On-chip address counter, incremented by each rising
edge on the clock input
• Simple interface to the FPGA; requires only one user
I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active Low)
for compatibility with different FPGA solutions
• Supports XC4000EX/XL fast configuration mode (15.0
MHz)
• Low-power CMOS Floating Gate process
• Available in 5 V and 3.3 V versions
• Available in compact plastic packages: 8-pin PDIP,
20-pin SOIC, and 20-pin PLCC.
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages.
Description
The XC1701L, XC1701 and XC17512L serial configuration
PROMs (SCPs) provide an easy-to-use, cost-effective
method for storing Xilinx FPGA configuration bitstreams.
When the FPGA is in master serial mode, it generates a
configuration clock that drives the SCP. A short access time
after the rising clock edge, data appears on the SCP DATA
output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
SCP. When the FPGA is in slave mode, the SCP and the
FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all SCPs in this chain
are interconnected. All devices are compatible and can be
cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to the programmer.
VCC VPP GND
CE
RESET/
OE or
OE/
RESET
CLK
Address Counter
TC
EPROM
Cell
Matrix
Output
Figure 1: Simplified Block Diagram (does not show programming circuit)
CEO
OE
DATA
X3185
December 10, 1997 (Version 1.1)
5-1
1 page  
Standby Mode
The PROM enters a low-power standby mode whenever
CE is asserted High. The output remains in a high imped-
ance state regardless of the state of the OE input.
Programming
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
Table 1: Truth Table for XC1700 Control Inputs
Control Inputs
RESET
Inactive
CE
Low
Active
Inactive
Active
Low
High
High
Internal Address
if address < TC: increment
if address > TC: don’t change
Held reset
Not changing
Held reset
DATA
active
3-state
3-state
3-state
3-state
Notes: 1. The XC1700 RESET input has programmable polarity
2. TC = Terminal Count = highest address value. TC+1 = address 0.
Outputs
CEO
High
Low
High
High
High
Icc
active
reduced
active
standby
standby
IMPORTANT: Always tie the VPP pin to VCC in your application. Never leave VPP floating.
December 10, 1997 (Version 1.1)
5-5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet XC1701.PDF ] | |
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