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XA-SCC Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer XA-SCC
Beschreibung CMOS 16-bit communications microcontroller
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
XA-SCC Datasheet, Funktion
INTEGRATED CIRCUITS
XA-SCC
CMOS 16-bit communications
microcontroller
Preliminary specification
Supersedes data of 1999 Feb 23
IC25 Data Handbook
1999 Mar 29
Philips
Semiconductors






XA-SCC Datasheet, Funktion
Philips Semiconductors
CMOS 16-bit communications microcontroller
Preliminary specification
XA-SCC
PIN DESCRIPTIONS
MNEMONIC
LQFP
PIN NO.
TYPE
NAME AND FUNCTION
VSS
1, 19,
I Ground: 0V reference.
28, 44,
59, 76,
88
VDD
2, 20,
I Power Supply: This is the power supply voltage for normal, idle, and power down operation.
29, 43,
62, 77,
89
ResetIn
55 I Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their
default states, and the processor to begin execution at the address contained in the reset vector.
WAIT/Size16
52
I Wait/Size16: During Reset, this input determines bus size for boot device (1 = 16 bit boot device,
0 = 8 bit.) During normal operation this is the Wait input (1 = Wait, 0 = Proceed.)
XTALIn
60 I Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal clock
generator circuits.
XTALOut
61 I Crystal 2: Output from the oscillator amplifier.
CS0 49 O Chip Select 0: This output provides the active low chip select to the boot device (usually ROM or
Flash.) It cannot be connected to DRAM. From reset, it is enabled and mapped to an address range
based at 000000h. It can be remapped to a higher base in the address map (see the Memory Interface
chapter in the XA-SCC User Manual.)
CS1_RAS1 48 O Chip Select 1 , RAS 1: Chip selects 1 through 5 come out of reset disabled. They can be programmed
to function as normal chip selects, or as RAS strobes to DRAM. CS1 can be “swapped” with CS0
(see the SWAP operation and control bit in the Memory Controller chapter of the XA-SCC
User Manual.) CS1 is usually mapped to be based at 000000h eventually, but is capable of being based
anywhere in the 16MB space.
CS2_RAS2 47 O CS2 , RAS 2: Active low chip selects CS1 through CS5 come out of reset disabled. They can be
programmed to function as normal chip selects, or as RAS strobes to DRAM. CS2 through CS5 are
not used with the “SWAP” operation (see Memory Controller chapter in the XA-SCC User Manual.)
They are mappable to any region of the 16MB address space.
CS3_RAS3 46 O CS3, RAS 3: See chip select 2 for description.
see pins 56,57 for 2 more chip
selects
WE 50 O Write Enable: Goes active low during all bus write cycles only.
OE 51 O Output Enable: Goes active low during all bus read cycles only.
BLE_CASL 54 O Byte Low Enable or CAS_Low_Byte: Goes active low during all bus cycles that access D7–D0, read
or write, Generic or DRAM. Functions as CAS during DRAM cycles.
BHE_CASH
53
O Byte High Enable or CAS_High_Byte: Goes active low during all bus cycles that access D15–D8,
read or write, Generic or DRAM. Functions as CAS during DRAM cycles.
ClkOut
45 O Clock Output: This pin outputs a buffered version of the internal CPU clock. The clock output may be
used in conjunction with the external bus to synchronize WAIT state generators, etc. The clock output
may be disabled by software. WARNING: The capacitive loading on this output must not exceed 40pF.
A19–A0
24–21,
18–3
O Address[19:0]: These address lines output a19–a0 during generic (SRAM etc) bus cycles. DRAMs are
connected only to pins 22,21, 18–10 (pins A17 to A7; see User Manual MIF Chapter for connecting
various DRAM sizes); the appropriate address values are multiplexed onto these 11 pins for RAS and
CAS during DRAM bus cycles.
D15–D0
P0.01
P0.11
P0.21
P0.31
P0.41, 2
42–30,
27–25
90
91
92
93
94
I/O Data[15:0]: Bi-directional data bus, D15–D0.
I/O P0.0_Sync0_BRG0_SDS2: Port 0 Bit 0, or SCC0 Sync input or output, or SCC0 BRG output, or SCC0
TxClk output, or IDL SDS2 output.
I/O P0.1_RTS0_L1RQ: Port0 Bit1 , or SCC0 RTS (Request to send) output, or IDL L1RQ (D Channel
Request) output.
I/O P0.2_CTS0_L1GR: Port 0 Bit2, or SCC0 CTS (Clear to Send) input or IDL L1GR (D Channel Grant)
input
I/O P0.3_CD0_L1SY1: Port 0 Bit 3, or SCC0 Carrier Detect input, or IDL Sync input.
I/O P0.4_TRClk0_SDS1: Port 0 Bit 4, or SCC0 TR clock input, or IDL SDS1 output.
1999 Mar 29
6

6 Page









XA-SCC pdf, datenblatt
Philips Semiconductors
CMOS 16-bit communications microcontroller
Preliminary specification
XA-SCC
MMR Name
SCC1 Write Register 13
SCC1 Write Register 14
SCC1 Write Register 15
SCC1 Write Register 16
SCC1 Write Register 17
SCC1 Read Register 0
SCC1 Read Register 1
Reserved
SCC1 Read Register 3
see WR16 and 17
SCC1 Read Register 6
SCC1 Read Register 7
SCC1 Read Register 8
Reserved
SCC1 Read Register 10
Reserved
SCC2 Write Register 0
SCC2 Write Register 1
SCC2 Write Register 2
SCC2 Write Register 3
SCC2 Write Register 4
SCC2 Write Register 5
SCC2 Write Register 6
SCC2 Write Register 7
SCC2 Write Register 8
SCC2 Write Register 9
SCC2 Write Register 10
SCC2 Write Register 11
SCC2 Write Register 12
SCC2 Write Register 13
SCC2 Write Register 14
SCC2 Write Register 15
SCC2 Write Register 16
SCC2 Write Register 17
SCC2 Read Register 0
SCC2 Read Register 1
Reserved
SCC2 Read Register 3
see WR16 and 17
SCC2 Read Register 6
SCC2 Read Register 7
SCC2 Read Register 8
Reserved
SCC2 Read Register 10
Reserved
1999 Mar 29
Read/Write or
Read Only
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
Size
Address
Offset
Description
8 85Ah Upper Byte of Baud rate time constant
8 85Ch Misc. Control bits
8 85Eh External/Status interrupt control
8 868h Match Character 2 (WR16)
8 86Ah Match Character 3 (WR17)
8 860h Tx/Rx buffer and external status
8 862h Receive condition status/residue code
864h
8 866h Interrupt Pending Bits
868–86Ah see WR16 and WR17 above
8 86Ch SDLC byte count low register
8 86Eh SDLC byte count high & FIFO status
8 870h Receive Buffer
872h
8 874h Loop/clock status
876–87Eh
SCC2 Registers
8 880h Command register
8 882h Tx/Rx Interrupt & data transfer mode
8 884h Extended Features Control
8 886h Receive Parameter and Control
8 888h Tx/Rx misc. parameters & mode
8 88Ah Tx. parameter and control
8 88Ch Sync character or SDLC address field or Match
Character 0
8 88Eh Sync character or SDLC flag or Match Character 1
8 890h Transmit Data Buffer
8 892h Master Interrupt control
8 894h Misc. Tx/Rx control register
8 896h Clock Mode Control
8 898h Lower Byte of Baud rate time constant
8 89Ah Upper Byte of Baud rate time constant
8 89Ch Misc. Control bits
8 89Eh External/Status interrupt control
8 8A8h Match Character 2 (wr16)
8 8AAh Match Character 3 (wr17)
8 8A0h Tx/Rx buffer and external status
8 8A2h Receive condition status/residue code
8A4h
8 8A6h Interrupt Pending Bits
8A8–8AAh see WR16 and WR17 above
8 8ACh SDLC byte count low register
8 8AEh SDLC byte count high & FIFO status
8 8B0h Receive Buffer
8B2h
8 8B4h Loop/clock status
8B6–8BEh
Reset
Value
00h
xx
f8h
00h
00h
00h
xx
xx
00h
00h
00h
00h
xx
xx
xx
00h
xx
00h
00h
xx
f8h
00h
00h
12

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