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PDF XA-G39 Data sheet ( Hoja de datos )
| Número de pieza | XA-G39 | |
| Descripción | XA 16-bit microcontroller family XA 16-bit microcontroller 32K FLASH/1K RAM/ watchdog/ 2 UARTs | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
XA-G39
XA 16-bit microcontroller family
32K FLASH/1K RAM, watchdog, 2 UARTs
Preliminary data
2002 Mar 13
Philips
Semiconductors
1 page  
Philips Semiconductors
XA 16-bit microcontroller family
32K Flash/1K RAM, watchdog, 2 UARTs
Preliminary data
XA-G39
PIN DESCRIPTION
MNEMONIC
PIN
NO.
TYPE
NAME AND FUNCTION
VSS
VDD
P0.0 – P0.7
1, 22
23, 44
43–36
I Ground: 0 V reference.
I Power Supply: This is the power supply voltage for normal, idle, and power down operation.
I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. Port 0 latches have 1s written to
them and are configured in the quasi-bidirectional mode during reset. The operation of port 0 pins as
inputs and outputs depends upon the port configuration selected. Each port pin is configured
independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for
details.
When the external program/data bus is used, Port 0 becomes the multiplexed low data/instruction byte and
address lines 4 through 11.
P1.0 – P1.7 2–9
2
3
4
5
6
7
8
9
I/O Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type. Port 1 latches have 1s written to
them and are configured in the quasi-bidirectional mode during reset. The operation of port 1 pins as
inputs and outputs depends upon the port configuration selected. Each port pin is configured
independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for
details.
Port 1 also provides special functions as described below.
O
A0/WRH:
Address bit 0 of the external address bus when the external data bus is configured for
an 8 bit width. When the external data bus is configured for a 16 bit width, this pin
becomes the high byte write strobe.
O A1:
O A2:
Address bit 1 of the external address bus.
Address bit 2 of the external address bus.
O A3:
Address bit 3 of the external address bus.
I RxD1 (P1.4): Receiver input for serial port 1.
O TxD1 (P1.5): Transmitter output for serial port 1.
I/O
T2 (P1.6):
Timer/counter 2 external count input/clockout.
I T2EX (P1.7): Timer/counter 2 reload/capture/direction control
P2.0 – P2.7 24–31
I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. Port 2 latches have 1s written to
them and are configured in the quasi-bidirectional mode during reset. The operation of port 2 pins as
inputs and outputs depends upon the port configuration selected. Each port pin is configured
independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for
details.
When the external program/data bus is used in 16-bit mode, Port 2 becomes the multiplexed high
data/instruction byte and address lines 12 through 19. When the external program/data bus is used in 8-bit
mode, the number of address lines that appear on port 2 is user programmable.
P3.0 – P3.7 11,
13–19
11
13
14
15
16
17
18
19
I/O Port 3: Port 3 is an 8-bit I/O port with a user configurable output type. Port 3 latches have 1s written to
them and are configured in the quasi-bidirectional mode during reset. the operation of port 3 pins as inputs
and outputs depends upon the port configuration selected. Each port pin is configured independently.
Refer to the section on I/O port configuration and the DC Electrical Characteristics for details.
Port 3 also provides various special functions as described below.
I
RxD0 (P3.0):
Receiver input for serial port 0.
O
TxD0 (P3.1):
Transmitter output for serial port 0.
I
INT0 (P3.2):
External interrupt 0 input.
I
INT1 (P3.3):
External interrupt 1 input.
I/O T0 (P3.4):
Timer 0 external input, or timer 0 overflow output.
I/O T1/BUSW (P3.5): Timer 1 external input, or timer 1 overflow output. The value on this pin is latched
as the external reset input is released and defines the default external data bus
width (BUSW). 0 = 8-bit bus and 1 = 16-bit bus.
O
WRL (P3.6):
External data memory low byte write strobe.
O RD (P3.7):
External data memory read strobe.
RST
10 I Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their
default states, and the processor to begin execution at the address contained in the reset vector. Refer to
the section on Reset for details.
ALE 33 I/O Address Latch Enable: A high output on the ALE pin signals external circuitry to latch the address portion
of the multiplexed address/data bus. A pulse on ALE occurs only when it is needed in order to process a
bus cycle.
2002 Mar 13
5
5 Page 
Philips Semiconductors
XA 16-bit microcontroller family
32K Flash/1K RAM, watchdog, 2 UARTs
Preliminary data
XA-G39
7FFF
BLOCK 2
16 KBYTES
PROGRAM
ADDRESS
4000
BLOCK 1
2000
8 KBYTES
BLOCK 0
0000
8 KBYTES
SU01591
Figure 3. Flash Memory Configuration
FMIDLE
The FMIDLE bit in the AUXR register allows saving additional power
by turning off the Flash memory when the CPU is in the Idle mode.
This must be done just prior to initiating the Idle mode, as shown
below.
OR AUXR,#$40
OR PCON,#$01
..
; Set Flash memory
to idle mode.
; Turn on Idle mode.
; Execution resumes
here when Idle
mode terminates.
When the Flash memory is put into the Idle mode by setting FMIDLE,
restarting the CPU upon exiting Idle mode takes slightly longer,
about 3 microseconds. However, the standby current consumed by
the Flash memory is reduced from about 8mA to about 1mA.
Default Loader
A default loader that accepts programming commands in a
predetermined format is contained permanently in the Boot ROM. A
factory fresh device will enter this loader automatically if it is
powered up without first being programmed by the user. Loader
commands include functions such as erase block; program Flash
memory; read Flash memory; and blank check.
Boot Vector
The XA-G39 contains two special FLASH registers: the BOOT
VECTOR and the STATUS BYTE.
The “Boot Vector” allows forcing the execution of a user supplied
Flash loader upon reset, under two specific sets of conditions. At the
falling edge of reset, the XA-G39 examines the contents of the
Status Byte. If the Status Byte is set to zero, power-up execution
starts at location 0000H, which is the normal start address of the
user’s application code.
When the Status Byte is set to a value other than zero, the Boot
Vector is used as the reset vector (4 bytes), including the Boot
Program Counter (BPC) and the Boot PSW (BPSW). The factory
default settings are 8000h for the BPSW and F800h for the BPC,
which corresponds to the address F900h for the factory masked-ROM
ISP boot loader. The Status Byte is automatically set to a non-zero
value when a programming error occurs. A custom boot loader can
be written with the Boot Vector set to the custom boot loader.
NOTE: When erasing the Status Byte or Boot Vector, these
bytes are erased at the same time. It is necessary to reprogram
the Boot Vector after erasing and updating the Status Byte.
Hardware Activation of the Boot Vector
Program execution at the Boot Vector may also be forced from
outside of the microcontroller by setting the correct state on a few
pins. While Reset is asserted, the PSEN pin must be pulled low, the
ALE pin allowed to float high (need not be pulled up externally), and
the EA pin driven to a logic high (or up to VPP). Then reset may be
released. This is the same effect as having a non-zero status byte.
This allows building an application that will normally execute the end
user’s code but can be manually forced into ISP operation. The Boot
ROM is enabled when use of the Boot Vector is forced as described
above, so the branch may go to the default loader. Conversely, user
code in the program memory space from F800h to FFFFh may not
be executed when the Boot Vector is used.
If the factory default setting for the BPC (F800h) is changed, it will
no longer point to the ISP masked-ROM boot loader code. If this
happens, the only possible way to change the contents of the Boot
Vector is through the parallel programming method, provided that
the end user application does not contain a customized loader that
provides for erasing and reprogramming of the Boot Vector and
Status Byte.
After programming the FLASH, the status byte should be erased to
zero in order to allow execution of the user’s application code
beginning at address 0000H.
2002 Mar 13
11
11 Page | ||
| Páginas | Total 42 Páginas | |
| PDF Descargar | [ Datasheet XA-G39.PDF ] | |
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