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X9521 Schematic ( PDF Datasheet ) - Xicor

Teilenummer X9521
Beschreibung Dual DCP/ EEPROM Memory
Hersteller Xicor
Logo Xicor Logo 




Gesamt 26 Seiten
X9521 Datasheet, Funktion
Hot Pluggable
Preliminary Information
X9521
Fiber Channel / Gigabit Ethernet Laser Diode Control for Fiber Optic Modules
Dual DCP, EEPROM Memory
FEATURES
• Two Digitally Controlled Potentiometers (DCP’s)
—100 Tap - 10k
—256 Tap - 100k
— Non-Volatile
—Write Protect Function
• 2 kbit EEPROM Memory with Write Protect & Block
LockTM
• 2-Wire industry standard Serial Interface
—Complies to the Gigabit Interface Converter (GBIC)
specification
• Single Supply Operation
—2.7V to 5.5V
• Hot Pluggable
• Packages
—CSP (Chip Scale Package)
—20 Pin TSSOP
DESCRIPTION
The X9521 combines two Digitally Controlled Potentiome-
ters (DCP’s), and integrated EEPROM with Block LockTM
protection. All functions of the X9521 are accessed by an
industry standard 2-Wire serial interface.
The DCP’s of the X9521 may be utilized to control the bias
and modulation currents of the laser diode in a Fiber Optic
module. The 2 kbit integrated EEPROM may be used to
store module definition data.
The features of the X9521 are ideally suited to simplifying
the design of fiber optic modules which comply to the Giga-
bit Interface Converter (GBIC) specification. The integration
of these functions into one package significantly reduces
board area, cost and increases reliability of laser diode
modules.
BLOCK DIAGRAM
WP
SDA
SCL
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
THRESHOLD
RESET LOGIC
8
PROTECT LOGIC
CONSTAT
REGISTER
4
2 kbit
EEPROM
ARRAY
©2000 Xicor Inc., Patents Pending
REV 1.1.9 1/30/03
www.xicor.com
WIPER
COUNTER
REGISTER
7 - BIT
NONVOLATILE
MEMORY
WIPER
COUNTER
REGISTER
8 - BIT
NONVOLATILE
MEMORY
RH1
RW1
RL1
RH2
RW2
RL2
Characteristics subject to change without notice. 1 of 26






X9521 Datasheet, Funktion
X9521 – Preliminary Information
Vcc
Vcc (Max.)
VTRIP
ttrans
tpu
t
0
Maximum Wiper Recall time
Figure 7. DCP Power up
before break” sequence is used internally for the FET
switches when the wiper is moved from one tap position
to another.
Hot Pluggability
Figure 7 shows a typical waveform that the X9521 might
experience in a Hot Pluggable situation. On power up,
Vcc applied to the X9521 may exhibit some amount of
ringing, before it settles to the required value.
The device is designed such that the wiper terminal (RWx)
is recalled to the correct position (as per the last stored in
the DCP NVM), when the voltage applied to Vcc exceeds
VTRIP for a time exceeding tpu.
Therefore, if ttrans is defined as the time taken for Vcc to
settle above VTRIP (Figure 7): then the desired wiper ter-
minal position is recalled by (a maximum) time: ttrans +
tpu. It should be noted that ttrans is determined by system
hot plug conditions.
DCP Operations
In total there are three operations that can be performed
on any internal DCP structure:
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
A nonvolatile write to a DCP will change the “wiper
position” by simultaneously writing new data to the
associated WCR and NVM. Therefore, the new “wiper
position” setting is recalled into the WCR after Vcc of the
X9521 is powered down and then powered back up.
A volatile write operation to a DCP however, changes the
“wiper position” by writing new data to the associated
WCR only. The contents of the associated NVM register
remains unchanged. Therefore, when Vcc to the device is
powered down then back up, the “wiper position” reverts
to that last position written to the DCP using a nonvolatile
write operation.
Both volatile and nonvolatile write operations are
executed using a three byte command sequence: (DCP)
Slave Address Byte, Instruction Byte, followed by a Data
Byte (See Figure 9)
A DCP Read operation allows the user to “read out” the
current “wiper position” of the DCP, as stored in the
associated WCR. This operation is executed using the
Random Address Read command sequence, consisting
of the (DCP) Slave Address Byte followed by an
Instruction Byte and the Slave Address Byte again (Refer
to Figure 10.).
Instruction Byte
While the Slave Address Byte is used to select the DCP
devices, an Instruction Byte is used to determine which
DCP is being addressed.
The Instruction Byte (Figure 8) is valid only when the
Device Type Identifier and the Internal Device Address
bits of the Slave Address are set to 1010111. In this
case, the two Least Significant Bit’s (I1 - I0) of the
Instruction Byte are used to select the particular DCP (0
- 2). In the case of a Write to any of the DCPs (i.e. the LSB
of the Slave Address is 0), the Most Significant Bit of the
Instruction Byte (I7), determines the Write Type (WT) per-
formed.
If WT is “1”, then a Nonvolatile Write to the DCP occurs. In
this case, the “wiper position” of the DCP is changed by
simultaneously writing new data to the associated WCR
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Characteristics subject to change without notice. 6 of 26

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X9521 pdf, datenblatt
X9521 – Preliminary Information
CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0
0 0 0 BL1 BL0 RWEL WEL 0
NV NV
Bit(s)
CS7 - CS5
BL1 - BL0
RWEL
WEL
CS0
Description
Always “0”(RESERVED)
Sets the Block Lock partition
Register Write Enable Latch bit
Write Enable Latch bit
Always “0” (RESERVED)
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
Figure 17. CONSTAT Register Format
ter now responds with an ACKNOWLEDGE, indicating it
requires additional data. The X9521 continues to output a
Data Byte for each ACKNOWLEDGE received. The mas-
ter terminates the read operation by not responding with
an ACKNOWLEDGE and instead issuing a STOP condi-
tion.
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through the entire
memory contents to be serially read during one operation.
At the end of the address space the counter “rolls over” to
address 00h and the device continues to output data for
each ACKNOWLEDGE received (Refer to Figure 16.).
CONTROL AND STATUS REGISTER
The Control and Status (CONSTAT) Register provides the
user with a mechanism for changing and reading the sta-
tus of various parameters of the X9521 (See Figure 17).
The CONSTAT register is a combination of both volatile
and nonvolatile bits. The nonvolatile bits of the CONSTAT
register retain their stored values even when Vcc is pow-
ered down, then powered back up. The volatile bits how-
ever, will always power up to a known logic state “0”
(irrespective of their value at power down).
A detailed description of the function of each of the CON-
STAT register bits follows:
WEL: Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of the entire
X9521 device. This bit must first be enabled before ANY
write operation (to DCPs, EEPROM memory array, or the
CONSTAT register). If the WEL bit is not first enabled,
then ANY proceeding (volatile or nonvolatile) write opera-
tion to DCPs, EEPROM array, as well as the CONSTAT
register, is aborted and no ACKNOWLEDGE is issued
after a Data Byte.
The WEL bit is a volatile latch that powers up in the dis-
abled, LOW (0) state. The WEL bit is enabled / set by writ-
ing 00000010 to the CONSTAT register. Once enabled,
the WEL bit remains set to “1” until either it is reset to “0”
(by writing 00000000 to the CONSTAT register) or until
the X9521 powers down, and then up again.
Writes to the WEL bit do not cause an internal high volt-
age write cycle. Therefore, the device is ready for another
operation immediately after a STOP condition is executed
in the CONSTAT Write command sequence (See Figure
18).
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9521. Therefore, in order to write to
any of the bits of the CONSTAT Register (except WEL),
the RWEL bit must first be set to “1”. The RWEL bit is a
volatile bit that powers up in the disabled, LOW (“0”) state.
It must be noted that the RWEL bit can only be set, once
the WEL bit has first been enabled (See "CONSTAT Reg-
ister Write Operation").
The RWEL bit will reset itself to the default “0” state, in
one of three cases:
—After a successful write operation to any bits of the
CONSTAT register has been completed (See Figure
18).
—When the X9521 is powered down.
—When attempting to write to a Block Lock protected
region of the EEPROM memory (See "BL1, BL0: Block
Lock protection bits - (Nonvolatile)", below).
BL1, BL0: Block Lock protection bits - (Nonvolatile)
The Block Lock protection bits (BL1 and BL0) are used to:
—Inhibit a write operation from being performed to certain
addresses of the EEPROM memory array
—Inhibit a DCP write operation (changing the “wiper posi-
tion”).
REV 1.1.9 1/30/03
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Characteristics subject to change without notice. 12 of 26

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