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PDF X9420 Data sheet ( Hoja de datos )
| Número de pieza | X9420 | |
| Descripción | Single Digitally Controlled (XDCP) Potentiometer | |
| Fabricantes | Xicor | |
| Logotipo |  |
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APPLICATION NOTES
AVAILABLE
AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
Low Noise/Low Power/SPI Bus
X9420
Single Digitally Controlled (XDCP) Potentiometer
FEATURES
• Solid-State Potentiometer
• SPI serial interface
• Register oriented format
—Direct read/write/transfer wiper positions
—Store as many as four positions per
potentiometer
• Power supplies
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = –2.7V to –5.5V
• Low power CMOS
—Standby current < 1µA
• High reliability
—Endurance–100,000 data changes per bit per
register
—Register data retention–100 years
• 8-bytes of nonvolatile EEPROM memory
• 10KΩ or 2.5KΩ resistor arrays
• Resolution: 64 taps each pot
• 14-lead TSSOP, 16-lead SOIC, and 16-pin plastic
DIP packages
DESCRIPTION
The X9420 integrates a single digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents of
the WCR controls the position of the wiper on the
resistor array through the switches. Power up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
HOLD
CS
SCK
S0
SI
A0
Interface
and
Control
Circuitry
8
Data
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VH/RH
VL/RL
VW/RW
REV 1.1.6 7/30/02
www.xicor.com
Characteristics subject to change without notice. 1 of 20
1 page  
X9420
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select one
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last two bits
are defined as 0.
Two of the eight instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
– XFR Data Register to Wiper Counter Register —This
instruction transfers the contents of one specified
Data Register to the Wiper Counter Register.
– XFR Wiper Counter Register to Data Register—This
instruction transfers the contents of the Wiper
Counter Register to the specified associated Data
Register.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between the potentiometer and one of its associated
registers.
Figure 4. Two-Byte Instruction Sequence
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9420; either between the host and one
of the Data Registers or directly between the host and
the WCR. These instructions are:
– Read Wiper Counter Register—read the current
wiper position of the pot,
– Write Wiper Counter Register—change current wiper
position of the pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
The sequence of these operations is shown in Figure 5
and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse (tHIGH)
while SI is HIGH, the selected wiper will move one
resistor segment towards the VH/RH terminal. Similarly,
for each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the
VL/RL terminal. A detailed illustration of the sequence
and timing for this operation are shown in Figure 7 and
Figure 8.
CS
SCK
SI
0 1 0 1 1 1 0 A0 I3 I2 I1 I0 R1 R0 0 0
REV 1.1.6 7/30/02
www.xicor.com
Characteristics subject to change without notice. 5 of 20
5 Page 
X9420
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Symbol
Parameter
ICC1 VCC Supply Current (Active)
Min.
Limits
Typ. Max.
400
ICC2
ISB
ILI
ILO
VIH
VIL
VOL
VCC Supply Current
(Non-volatile Write)
VCC Current (Standby)
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
Output LOW Voltage
VCC x 0.7
–0.5
1
1
10
10
VCC + 0.5
VCC x 0.1
0.4
Units
µA
mA
µA
µA
µA
V
V
V
Test Conditions
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
SCK = SI = VSS, Addr. = VSS
VIN = VSS to VCC
VOUT = VSS to VCC
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Minimum Endurance
Data Retention
Min.
100,000
100
Units
Data Changes per Bit per Register
Years
CAPACITANCE
Symbol
COUT(5)
CIN(5)
Test
Output Capacitance (SO)
Input Capacitance (A0, SI, and SCK)
Max.
8
6
Units
pF
pF
Test Conditions
VOUT = 0V
VIN = 0V
POWER-UP TIMING
Symbol
tPUR(6)
tPUW(6)
tRVCC
Parameter
Power-up to Initiation of Read Operation
Power-up to Initiation of Write Operation
VCC Power up Ramp
Max.
1
5
0.2
Max.
1
5
50
Units
ms
ms
V/msec
POWER UP REQUIREMENTS (Power up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First VCC, then V+ and V–, and then the potentiometer pins, RH,
RL, and RW. Voltage should not be applied to the potentiometer pins before V+ or V– is applied. The VCC ramp rate
specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if
possible. If VCC powers down, it should be held below 0.1V for more than 1 second before powering up again in
order for proper wiper register recall. Also, VCC should not reverse polarity by more than 0.5V. Recall of wiper
position will not be complete until VCC, V+ and V– reach their final value.
Notes: (5) This parameter is periodically sampled and not 100% tested.
(6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific
instruction can be issued. These parameters are periodically sampled and not 100% tested.
REV 1.1.6 7/30/02
www.xicor.com
Characteristics subject to change without notice. 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet X9420.PDF ] | |
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