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X930A Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer X930A
Beschreibung UNIVERSAL SERIAL BUS MICROCONTROLLER
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
X930A Datasheet, Funktion
ADVANCE INFORMATION
8x930Ax
UNIVERSAL SERIAL BUS
MICROCONTROLLER
s Complete Universal Serial Bus
Specification 1.0 Compatibility
— Supports Isochronous and
Non-isochronous Data
— Bidirectional Half-duplex Link
s On-chip USB Transceiver
s Serial Bus Interface Engine (SIE)
— Packet Decoding/Generation
— CRC Generation and Checking
— NRZI Encoding/Decoding and
Bit-stuffing
s USB Reset Interrupt
s Four Transmit FIFOs
— Three 16-byte FIFOs
— One Configurable FIFO (up to
1 Kbyte)
s Four Receive FIFOs
— Three 16-byte FIFOs
— One Configurable FIFO (up to
1 Kbyte)
s Automatic Transmit/Receive FIFO
Management
s Suspend/Resume Operation
s Three New USB Interrupt Vectors
— USB Function Interrupt
— Start of Frame
— Suspend/Resume
s Phase-locked Loop
— 12 Mbps or 1.5 Mbps Data Rate
s Low Clock Mode
s User-selectable Configurations
— External Wait State
— Address Range
— Page Mode
s Real-time Wait Function
s 256-Kbyte External Code/Data Memory
Space
s On-chip ROM Options
— 0, 8, or 16 Kbytes
s 1 Kbyte On-chip Data RAM
s Four Input/Output Ports
— 1 Open-drain port
— 3 Quasi-bidirectional Ports
s Programmable Counter Array (PCA)
— 5 Capture/Compare Modules
s Serial I/O Port (UART)
s Hardware Watchdog Timer
s Three Flexible 16-bit Timer/Counters
s Power-saving Idle and Powerdown
Modes
s Register-based MCS® 251 Architecture
— 40-byte Register File
— Registers Accessible as Bytes,
Words, or Doublewords
s Code Compatible with MCS 51 and MCS
251 Microcontrollers
s 6 or 12 MHz Crystal Operation
The 8x930Ax USB microcontroller is based on an 8xC251Sx microcontroller core. It consists of standard
8xC251Sx peripherals plus an added USB function. The 8x930Ax uses the standard instruction set of the
MCS 251 architecture, which is binary code compatible with the MCS 51 architecture. The USB function
integrates the USB transceiver, serial bus interface engine (SIE), function interface unit (FIU) and
transmit/receive FIFOs. The USB function also supports full-speed/low-speed data rates, suspend/resume
modes, isochronous/non-isochronous transfers, and is fully compliant with the USB rev 1.0 specification.
COPYRIGHT © INTEL CORPORATION, 1997
February 1997
Order Number: 272917-003






X930A Datasheet, Funktion
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
To
CPU
USB
Upstream
Port
Transceiver
Serial Bus
Interface Engine
(SIE)
Control
Control
Function
Interface Unit
(FIU)
Control
FIFOs
Figure 2. USB Module Block Diagram
A4231-03
2 ADVANCE INFORMATION

6 Page









X930A pdf, datenblatt
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 5. Signal Descriptions (Continued)
Signal
Name
Type
Description
Alternate Function
P1.0
P1.1
P1.2
P1.5:3
P1.6
P1.7
I/O Port 1. This is an 8-bit, bidirectional I/O port with internal
pullups.
T2
T2EX
ECI
CEX2:0
CEX3/WAIT#
CEX4/A17/WCLK
P2.7:0
I/O Port 2. This is an 8-bit, bidirectional I/O port with internal
pullups.
A15:8
P3.0
P3.1
P3.3:2
P3.5:4
P3.6
P3.7
I/O Port 3. This is an 8-bit, bidirectional I/O port with internal
pullups.
RXD
TXD
INT1:0#
T1:0
WR#
RD#/A16
PLLSEL2:0
I Phase-locked Loop Select. Three-bit code selects USB
data rate (see Table 8 on page 12).
PSEN#
O Program Store Enable. Read signal output. This output is —
asserted for a memory address range that depends on bits
RD0 and RD1 in configuration byte UCONFIG0 (see RD#).
RD#
O Read or 17th Address Bit (A16). Read signal output to
P3.7/A16
external data memory or 17th external address bit (A16),
depending on the values of bits RD0 and RD1 in configura-
tion byte UCONFIG0 (See PSEN#).
RST
I Reset. Reset input to the chip. Holding this pin high for 64 —
oscillator periods while the oscillator is running resets the
device. The port pins are driven to their reset conditions
when a voltage greater than VIH1 is applied, whether or not
the oscillator is running. This pin has an internal pulldown
resistor which allows the device to be reset by connecting a
capacitor between this pin and VCC.
Asserting RST when the chip is in idle mode or powerdown
mode returns the chip to normal operation.
RXD
I/O Receive Serial Data. RXD sends and receives data in
P3.0
serial I/O mode 0 and receives data in serial I/O modes 1, 2,
and 3.
SOF#
O Start of Frame. Start of Frame pulse. Active low, asserted —
for 8 states (see Table 8 on page 12 for state versus XTAL
clock) when Frame Timer is locked to USB frame timing
and SOF token or artificial SOF is detected.
T1:0
I Timer 1:0 External Clock Inputs. When timer 1:0 operates P3.5:4
as a counter, a falling edge on the T1:0 pin increments the
count.
T2 I/O Timer 2 Clock Input/Output. For the timer 2 capture mode, P1.0
this signal is the external clock input. For the clock-out
mode, it is the timer 2 clock output.
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration. If the
chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 car-
ries the upper address bits (A15:8) and the data (D7:0).
8 ADVANCE INFORMATION

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