PDF X9271 Data sheet ( Hoja de datos )

Número de pieza	X9271
Descripción	Single Digitally-Controlled (XDCP) Potentiometer
Fabricantes	Xicor
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No Preview Available ! APPLICATION NOTES AND DEVELOPMENT SYSTEM AVAILABLE AN99 • AN115 • AN124 •AN133 • AN134 • AN135 Single Supply / Low Power / 256-tap / SPI bus X9271 Single Digitally-Controlled (XDCPTM) Potentiometer FEATURES • 256 Resistor Taps • SPI Serial Interface for write, read, and transfer operations of the potentiometer • Wiper Resistance, 100Ω typical @ VCC = 5V • 16 Nonvolatile Data Registers • Nonvolatile Storage of Multiple Wiper Positions • Power On Recall. Loads Saved Wiper Position on Power Up. • Standby Current < 3µA Max • VCC: 2.7V to 5.5V Operation • 50KΩ, 100KΩ versions of End to End Resistance • 100 yr. Data Retention • Endurance: 100,000 Data Changes per Bit per Register • 14-Lead TSSOP, 16-Lead CSP (Chip Scale Package) • Low Power CMOS DESCRIPTION The X9271 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four nonvolatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. FUNCTIONAL DIAGRAM VCC SPI Bus Interface Address Data Status Bus Interface and Control Write Read Transfer Inc/Dec Control Power On Recall Wiper Counter Register (WCR) Data Registers 16 Bytes RH 50KΩ and 100KΩ 256-taps POT VSS RW RL REV 1.1.7 2/6/03 www.xicor.com Characteristics subject to change without notice. 1 of 23 1 page X9271 PRINCIPLES OF OPERATION Device Description SERIAL INTERFACE The X9271 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. ARRAY DESCRIPTION The X9271 is comprised of a resistor array (see Figure 1). The array contains the equivalent of 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the ﬁxed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to select, and enable, one of 256 switches (see Table 1). POWER UP AND DOWN RECOMMENDATIONS. There are no restrictions on the power-up or power- down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC ramp rate speciﬁcation is always in effect. Figure 1. Detailed Potentiometer Block Diagram SERIAL DATA PATH FROM INTERFACE CIRCUITRY REGISTER 0 (DR0) 8 REGISTER 1 (DR1) 8 BANK_0 Only REGISTER 2 (DR2) REGISTER 3 (DR3) SERIAL BUS INPUT PARALLEL BUS INPUT WIPER COUNTER REGISTER (WCR) IF WCR = 00[H] THEN RW = RL IF WCR = FF[H] THEN RW = RH UP/DN MODIFIED SCK INC/DEC LOGIC UP/DN CLK C O U N T E R D E C O D E RH RL RW REV 1.1.7 2/6/03 www.xicor.com Characteristics subject to change without notice. 5 of 23 5 Page X9271 INSTRUCTION FORMAT Read Wiper Counter Register (WCR) CS Falling Edge Device Type Identifier 0101 Device Addresses 0 0 A1 A0 Instruction Opcode 1001 DR/Bank Wiper Position Addresses (Sent by X9271 on SO) CS W W W W W W W W Rising 0 0 0 0 C R C R C R C R C R C R C R C R Edge 76543210 Write Wiper Counter Register (WCR) CS Falling Edge Device Type Identifier 0101 Device Addresses 0 0 A1 A0 Instruction Opcode 1010 DR/Bank Addresses 00 0 0 Data Byte (Sent by Host on SI) CS W W W W W W W W Rising C C C C C C C C Edge RRRRRRRR 76543210 Read Data Register (DR) CS Device Type Device Instruction DR/Bank Data Byte CS Falling Identifier Addresses Opcode Addresses (Sent by X9271 on SO) Rising Edge 0 1 0 1 0 0 A1 A0 1 0 1 1 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0 Edge Write Data Register (DR) Device Type Device Instruction DR/Bank Data Byte CS Falling Edge Identifier 0101 Addresses 0 0 A1 A0 Opcode Addresses (Sent by Host on SI) 1 1 0 0 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0 CS Rising Edge Transfer Wiper Counter Register (WCR) to Data Register (DR) CS Device Type Falling Identifier Edge 0 1 0 1 Device Instruction Addresses Opcode 0 0 A1 A0 1 1 1 0 DR/Bank Addresses RB RA 0 0 CS Rising Edge HIGH-VOLTAGE WRITE CYCLE REV 1.1.7 2/6/03 www.xicor.com Characteristics subject to change without notice. 11 of 23 11 Page

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