X88064S-60 Datasheet PDF - Xicor
| Part Number | X88064S-60 | |
| Description | E2 Micro-Peripheral | |
| Manufacturers | Xicor | |
| Logo |  |
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APPLICATION NOTE
A V A I LABLE
Application Brief
iAPX88/188, MCS 196, MCS51 Compatible*
64K
X88064
8192 x 8 Bit
E2 Microcontroller Peripheral
• Block Lock Write Control
—Eight 1K Byte Blocks
- Lockable Independently or in Combination
• Multiplexed Address/Data Bus
—Direct Interface to Popular Microcontrollers
• High Performance CMOS
—Fast Access Times, 60ns and 80 ns
—Low Power
- 30mA Active Maximum
- 150µA Standby Maximum
• Software Data Protection
• Toggle Bit Polling
—Early End of Write Detection
• Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
DESCRIPTION
The X88064 is a high speed byte wide microperipheral
device with eight 1K byte blocks of E2PROM and can be
directly connected to industry standard high performance
microprocessors. This peripheral provides two levels of
memory write control, the standard Software Data Pro-
gram (SDP) control and Block Lock.
Block Lock provides a higher level of memory write con-
trol above SDP. This allows the software developer to
partition any or all of the eight 1K byte blocks as In-Circuit
Programmable ROM (ICPROM). Once locked, a block of
memory must first be unlocked before being written. Not
even a write operation using the SDP sequence will
change the contents of a locked block. Since a distinct, 6
byte, software command sequence locks and unlocks
the memory, the software developer has complete con-
trol of the memory contents.
ALE
A/D0–A/D7
A8–A12
L
A
T
C
H
WR
RD
PSEN
CE
WC
INTERFACE
CONTROL
BLOCK LOCK
CONTROL
LOGIC
D
E
C
O
D
E
R
INDIVIDUALLY LOCKABLE
E2 PROM
ARRAY
1Kx8 BLOCKS
SOFTWARE DATA PROTECT
(SDP)
WE
OE BUS TRANSCEIVER
POWER-ON RESET
AND VCC SENSE
A/D0–A/D7
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
* All other brand and product names may be trademarks or
registered trademarks of their respective companies.
7023-2.3 1/29/97 T0/C2/D0 SH
1
Characteristics subject to change without notice
|
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X88064
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X88064
supports page mode write operations. This allows the
microcontroller to write from one to thirty-two bytes of
data to the X88064. Each individual write within a page
write operation must conform to the byte write timing
requirements. The falling edge of WR starts a timer
delaying the internal programming cycle 100µs. There-
fore, each successive write operation must begin within
100µs of the last byte written. The following waveforms
illustrate the sequence and timing requirements.
Page Write Timing Sequence for WR Controller Operation
OPERATION
BYTE 0
BYTE 1
BYTE 2
LAST BYTE
CE
ALE
A/D0 –A/D 7
A8 –A12
AIN DIN
A12=n
AIN DIN
A12=n
AIN DIN
A12=n
AIN DIN
A12=n
WR
READ (1)
AIN DOUT
A12=x
AFTER tWC READY FOR
NEXT WRITE OPERATION
AIN
ADDR
AIN
Next Address
PSEN(RD)
tBLC
Notes: (1) For each successive write within a page write cycle A5–A12 must be the same.
tWC
7023 FRM F04
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for X88064S-60 electronic component. |
| Information | Total 15 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ X88064S-60.PDF Datasheet ] | |
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