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X86C64SM Schematic ( PDF Datasheet ) - Xicor

Teilenummer X86C64SM
Beschreibung E2 Micro-Peripheral
Hersteller Xicor
Logo Xicor Logo 




Gesamt 12 Seiten
X86C64SM Datasheet, Funktion
Preliminary Information
XZ8®6CM6ic4rocontroller Family Compatible
64K X86C64
E2 Micro-Peripheral
8192 x 8 Bit
FEATURES
CONCURRENT READ WRITE
—Dual Plane Architecture
Isolates Read/Write Functions
Between Planes
Allows Continuous Execution of Code
From One Plane While Writing in the Other
Plane
Multiplexed Address/Data Bus
—Direct Interface to Popular 8-bit
Microcontrollers, e.g. Zilog Z8 Family
High Performance CMOS
—Fast Access Time, 120 ns
—Low Power
60 mA Maximum Active
200 µA Maximum Standby
Software Data Protection
Block Protect Register
—Individually Set Write Lock Out in 1K Blocks
Toggle Bit
—Early End of Write Detection
Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
High Reliability
—Endurance: 10,000 Write Cycle
—Data Retention: 100 Years
DESCRIPTION
The X86C64 is an 8K x 8 E2PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X86C64 features a Multiplexed Address and
Data bus allowing direct interface to a variety of popular
single-chip microcontrollers operating in expanded mul-
tiplexed mode without the need for additional interface
circuitry.
The X86C64 is internally configured as two indepen-
dent 4K x 8 memory arrays. This feature provides the
ability to perform nonvolatile memory updates in one
array and continue operation out of code stored in the
other array; effectively eliminating the need for an aux-
iliary memory device for code storage.
To write to the X86C64, a three byte command
sequence must precede the byte(s) being written. The
X86C64 also provides a second generation software
data protection scheme called Block Protect. Block
Protect can provide write lockout of the entire device or
selected 1K blocks. There are eight, 1K x 8 blocks that
can be write protected individually in any combination
required by the user. Block Protect, in addition to Write
Control input, allows the different segments of the
memory to have varying degrees of alterability in nor-
mal system operation.
FUNCTIONAL DIAGRAM
CE
R/W
DS
SEL
A8–A11
AS
CONTROL
LOGIC
LX
AD
TE
CC
HO
ED
SE
WC
A12
SOFTWARE
DATA
PROTECT
A12
1K BYTES A12 1K BYTES
M
1K BYTES
1K BYTES
U
1K BYTES X 1K BYTES
1K BYTES
1K BYTES
Y DECODE
Z8® is a registered trademark of Zilog Corporation
CONCURRENT READ WRITEis a trademark of Xicor, Inc.
© Xicor, 1991 Patents Pending
3819-2.1 7/29/96 T0/C1/D1 SH
I/O & ADDRESS LATCHES AND BUFFERS
A/D0–A/D7
3819 FHD F02
1 Characteristics subject to change without notice






X86C64SM Datasheet, Funktion
X86C64
DATA PROTECTION
The X86C64 provides two levels of data protection
through software control. There is a global software data
protection feature similar to the industry standard for
E2PROMs and a new Block Protect write lock out
protection providing a second level data security option.
Writing with SDP
WRITE AA
TO X555
WRITE 55
TO XAAA
PERFORM BYTE
OR PAGE WRITE
OPERATIONS
WAIT tWC
WRITE A0
TO X555
EXIT ROUTINE
X = A12:
A12 = 1 IF DATA TO BE WRITTEN IS WITHIN
ADDRESS 1000 TO 1FFF.
A12 = 0 IF DATA TO BE WRITTEN IS WITHIN
ADDRESS 0000 TO 0FFF.
3819 FHD F09
Software Data Protection
Software data protection (SDP) is employed to protect
the entire array against inadvertent writes. To write to
the X86C64, a three byte command sequence must
precede the byte(s) being written.
All write operations, both the command sequence and
any data write operations must conform to the page write
timing requirements.
Block Protect Write Lockout
The X86C64 provides a second level of data security
referred to as Block Protect write lockout. This is ac-
cessed through an extension of the SDP command
sequence. Block Protect allows the user to lock out
writes to 1K x 8 blocks of memory. Unlike SDP which
prevents inadvertent writes, but still allows easy system
access to writing the memory, Block Protect will lock out
all attempts unless it is specifically disabled by the host.
This could be used to set a higher level of protection in
a system where a portion of the memory is used for
Program Store and another portion is used as Data
Store.
Setting write lockout is accomplished by writing a five
byte command sequence opening access to the Block
Protect Register (BPR). After the fifth byte is written the
user writes to the BPR selecting which blocks to protect
or unprotect. All write operations, both the command
sequence and writing the data to the BPR, must conform
to the page write timing requirements.
Block Protect Register Format
MSB
LSB
7654321 0
BLOCK
ADDRESS
0000–03FF
0400–07FF
0800–0BFF
0C00–0FFF
1000–13FF
1400–17FF
1800–1BFF
1C00–1FFF
1 = Protect, 0 = Unprotect Block Specified
3819 FHD F11
Setting BPR Command Sequence
WRITE AA
TO X555
WRITE C0
TO XAAA
WRITE 55
TO XAAA
WRITE A0
TO X555
WRITE BPR
MASK VALUE TO
ANY ADDRESS
WAIT tWC
WRITE AA
TO X555
EXIT ROUTINE
X = A12:
A12 = 1 IF PROGRAM BEING EXECUTED IS
WITHIN 0000 TO 0FFF.
A12 = 0 IF PROGRAM BEING EXECUTED
RESIDES WITHIN 1000 TO 1FFF.
3819 FHD F12
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X86C64SM pdf, datenblatt
X86C64
ORDERING INFORMATION
Device
X86C64 X X X
VCC Limits
Blank = 5V ± 10%
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +128°C
Package
P = 24-Lead Plastic DIP
S = 24-Lead Plastic SOIC
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
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