PDF ZL30407 Data sheet ( Hoja de datos )

Número de pieza	ZL30407
Descripción	SONET/SDH Network Element PLL
Fabricantes	Zarlink Semiconductor Inc
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ZL30407 SONET/SDH Network Element PLL Data Sheet Features • Meets requirements of GR-253 for SONET Stratum 3 and SONET Minimum Clocks (SMC) • Meets requirements of GR-1244 for Stratum 3 • Meets requirements of G.813 Option 1 and 2 for SDH Equipment Clocks (SEC) • Generates clocks for ST-BUS, DS1, DS2, DS3, OC-3, E1, E3, STM-1 and 19.44 MHz • Holdover accuracy of 4x10 -12 meets GR-1244 Stratum 3E and ITU-T G.812 requirements • Continuously monitors both references for frequency accuracy exceeding ±12 ppm • Provides “hit-less” reference switching • Compensates for Master Clock Oscillator accuracy • Automatically detects frequency of both reference clocks and synchronizes to any combination of 8 kHz, 1.544 MHz, 2.048 MHz and 19.44 MHz reference frequencies • Allows Hardware or Microprocessor control • Pin compatible with ZL30410, ZL30402 and MT90401 November 2004 Ordering Information ZL30407QCC 80 Pin LQFP Trays ZL30407QCC1 80 Pin LQFP* Trays *Pb Free Matte Tin -40°C to +85°C Applications • Synchronization for SDH and SONET Network Elements • Clock generation for ST-BUS and GCI backplanes Description The ZL30407 is a Network Element Phase-Locked Loop designed to synchronize SDH and SONET systems. In addition, it generates multiple clocks for legacy PDH equipment and provides timing for ST- BUS and GCI backplanes. VDD GND C20i FCS OE PRI PRIOR SEC SECOR RefSel HW RESET Primary Acquisition PLL Secondary Acquisition PLL Master Clock Frequency Calibration MUX Microport Core PLL APLL Clock Synthesizer Control State Machine JTAG IEEE 1149.1a CS DS R/W A0-A6 D0-D7 MS1 MS2 RefAlign LOCK HOLDOVER C155P/N C34/C44 C19o C16o C8o C6o C4o C2o C1.5o F16o F8o F0o E3DS3/OC3 E3/DS3 Tclk Tdi Tdo Tms Trst R1-17 Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. 1 page ZL30407 Data Sheet List of Tables Table 1 - Loop Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 2 - Operating Modes and States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 3 - Filter Characteristic Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 4 - Reference Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 5 - ZL30407 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 6 - Control Register 1 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 7 - Status Register 1 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 8 - Control Register 2 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 9 - Phase Offset Register 2 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 10 - Phase Offset Register 1 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 11 - Device ID Register (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 12 - Control Register 3 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 13 - Clock Disable Register 1 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 14 - Clock Disable Register 2 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 15 - Core PLL Control Register (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 16 - Fine Phase Offset Register (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 17 - Primary Acquisition PLL Status Register (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 18 - Secondary Acquisition PLL Status Register (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 19 - Master Clock Frequency Calibration Register 4 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 20 - Master Clock Frequency Calibration Register 3 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 21 - Master Clock Frequency Calibration Register 2 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 22 - Master Clock Frequency Calibration Register 1 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5 Zarlink Semiconductor Inc. 5 Page Pin Description (continued) Pin # 64 Name RESET 65 66-69 70 71 72 73 74 - 77 78 HW D0 - D3 GND IC IC VDD D4 - D7 R/W 79 A0 80 IC ZL30407 Data Sheet Description RESET (5 V tolerant input). The ZL30407 must be reset after power-up in order to set internal registers into a default state. The internal reset is performed by forcing RESET pin low for a minimum of 1 µs after the C20 Master Clock is applied to pin C20i. This operation forces the ZL30407 internal state machine into a RESET state for a duration of 625 µs. Hardware/Software Control (Input). If this pin it tied low, the ZL30407 is controlled via the microport. If it is tied high, the ZL30407 is controlled via the control pins MS1, MS2, FCS, RefSel, RefAlign, E3/DS3 and E3DS3/OC3. Data 0 to Data 3 (5 V tolerant three-state I/O). These ports combined with D4 - D7 ports form the bi-directional data bus of the microprocessor interface (D0 is the least significant bit). Ground Internal Connection (Input). Connect this pin to ground. Internal Connection (Input). Connect this pin to ground. Positive Power Supply Data 4 to Data 7 (5 V tolerant three-state I/O). These ports combined with D0 - D3 ports form the bi-directional data bus of the processor interface (D7 is the most significant bit). Read/Write Strobe (5 V tolerant input). This input controls the direction of the data bus D[0-7] during a microprocessor access. When R/W is high, the parallel processor is reading data from the ZL30407. When low, the parallel processor is writing data to the ZL30407. Address 0 (5 V tolerant input). Address input for the microprocessor interface. A0 is the least significant input. Internal Connection (Input). Connect this pin to ground. 11 Zarlink Semiconductor Inc. 11 Page

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