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ZL10312 Schematic ( PDF Datasheet ) - Zarlink Semiconductor Inc

Teilenummer ZL10312
Beschreibung Satellite Demodulator
Hersteller Zarlink Semiconductor Inc
Logo Zarlink Semiconductor Inc Logo 




Gesamt 15 Seiten
ZL10312 Datasheet, Funktion
ZL10312
Satellite Demodulator
Data Sheet
Features
• Conforms to EBU specification for DVB-S and
DirecTV specification for DSS
• On-chip digital filtering supports 1 - 45 MSps
symbol rates
• On-chip 60 or 90 MHz dual-ADC
• High speed scanning mode for blind symbol
rate/code rate acquisition
• Automatic spectral inversion resolution
• High level software interface for minimum
development time
• Up to ±22 MHz LNB frequency tracking
• DiSEqC™ v2.2: receive/transmit for full control of
LNB, dish and other components
• Compact 64 pin LQFP package (7 x 7 mm)
• Sleep pin gives ~1,000 fold reduction in power to
help products meet ENERGY STAR®
requirements
Applications
• DVB 1 - 45 MSps compliant satellite receiver
• DSS 20 MSps compliant satellite receivers
• SMATV trans-modulators. (Single Master
Antenna TV)
• Satellite PC applications
November 2004
Ordering Information
ZL10312QCG
ZL10312QCF
ZL10312QCG1
ZL10312UBH
64 Pin LQFP Trays, Bake & Drypack
64 Pin LQFP Tape & Reel
64 Pin LQFP* Trays, Bake & Drypack
Die supplied in wafer form**
*Pb Free Matte Tin
**Please contact Sales for further details
0°C to +70°C
Description
The ZL10312 is a QPSK/BPSK 1 - 45 MSps
demodulator and channel decoder for digital satellite
television transmissions to the European Broadcast
Union ETS 300 421 specification. It receives analogue
I and Q signals from the tuner, digitises and digitally
demodulates this signal, and implements the complete
DVB/DSS FEC (Forward Error Correction), and de-
scrambling function. The output is in the form of
MPEG2 or DSS transport stream data packets. The
ZL10312 also provides automatic gain control to the RF
front-end device.
The ZL10312 has a serial 2-wire bus interface to the
control microprocessor. Minimal software is required to
control the ZL10312 because of the built in automatic
search and decode control functions.
I I/P
Q I/P
Dual ADC
De-rotator
Decimation
Filtering
Timing recovery
Matched filter
Phase recovery
DVB
DSS
FEC
MPEG/
DSS
Packets
Analog
AGC
Control
Clock Generation
Acquisition
Control
2-Wire Bus Bus I/O
Interface
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.






ZL10312 Datasheet, Funktion
ZL10312
Data Sheet
1.0 Functional Overview
1.1 Introduction
ZL10312 is a single-chip variable rate digital QPSK/BPSK satellite demodulator and channel decoder. The
ZL10312 accepts base-band in-phase and quadrature analogue signals and delivers an MPEG or DSS packet data
stream. Digital filtering in ZL10312 removes the need for programmable external anti-alias filtering for all symbol
rates from 1 - 45 MSps. Frequency, timing and carrier phase recovery are all digital and the only feed-back to the
analogue front-end is for automatic gain control. The digital phase recovery loop enables very fine bandwidth
control that is needed to overcome performance degradation due to phase and thermal noise.
All acquisition algorithms are built into the ZL10312 controller. The ZL10312 can be operated in a Command Driven
Control (CDC) mode by specifying the symbol rate and Viterbi code rate. There is also a provision for a search for
unknown symbol rates and Viterbi code rates.
1.2 Analogue-to-Digital Converter and PLL
The A/D converters sample single-ended or differential analogue inputs and consist of a dual ADC and circuitry to
provide improved SiNaD (Signal-Noise and Distortion) and channel matching.
The fixed rate sampling clock is provided on-chip using a programmable PLL needing only a low cost 10 to 16 MHz
crystal. Different crystal frequencies can be combined with different PLL ratios, depending on the maximum symbol
rate, allowing a very flexible approach to clock generation. An external clock signal in the range 4 to 16 MHz can
also be used as the master clock.
1.3 QPSK Demodulator
The demodulator in the ZL10312 consists of signal amplitude offset compensation, frequency offset compensation,
decimation filtering, carrier recovery, symbol recovery and matched filtering. The decimation filters give continuous
operation from 2Mbits/s to 90Mbits/s allowing one receiver to cover the needs of the consumer market as well as
the single carrier per channel (SCPC) market with the same components without compromising performance, that
is, the channel reception is within 0.5dB of theoretical. For a given symbol rate, control algorithms on the chip
detect the number of decimation stages needed and switch them in automatically.
The frequency offset compensation circuitry is capable of tracking out up to ±22.5 MHz frequency offset. This
allows the system to cope with relatively large frequency uncertainties introduced by the Low Noise Block (LNB).
Full control of the LNB is provided by the DiSEqC outputs from the ZL10312. Horizontal/vertical polarisation and an
instruction modulated 22kHz signal are available under register control. All DiSEqC v2.x functions are implemented
on the ZL10312. An internal state machine that handles all the demodulator functions controls the signal acquisition
and tracking. Various pre-set modes are available as well as blind acquisition where the receiver has no prior
knowledge of the received signal. Fast acquisition algorithms have been provided for low symbol rate applications.
Full interactive control of the acquisition function is possible for debug purposes. In the event of a signal fade or a
cycle slip, the QPSK demodulator allows sufficient time for the FEC to re-acquire lock, for example, via a phase
rotation in the Viterbi decoder. This is to minimise the loss of signal due to the signal fade. Only if the FEC fails to
re-acquire lock for a long period (which is programmable) would QPSK try to re-acquire the signal.
The matched filter is a root-raised-cosine filter with either 0.20 or 0.35 roll-off, compliant with DSS and DVB
standards. Although not a part of the DVB standard, ZL10312 allows a roll-off of 0.20 to be used with other DVB
parameters. An AGC signal is provided to control the signal levels in the tuner section of the receiver and ensure
the signal level fed to the ZL10312 is set at an optimal value under all reception conditions.
The ZL10312 provides comprehensive information on the input signal and the state of the various parts of the
device. This information includes signal to noise ratio (SNR), signal level, AGC lock, timing and carrier lock signals.
A maskable interrupt output is available to inform the host controller when events occur.
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ZL10312 pdf, datenblatt
ZL10312
Data Sheet
Pin Description Table (continued)
Pin Name
Description
I/O Note
47
48,49,52,
53,56,
57,60,61
62
63
64
MOVAL
MDO[0:7]
MPEG data output valid. High during the MOCLK
cycles when valid data bytes are being output.
MPEG transport packet data output bus. Can be
tri-stated under control of a register bit.
O CMOS
Tri-state
O CMOS
Tri-state
MOCLK
BKERR
STATUS
MPEG clock output at the data byte rate.
O CMOS
Tri-state
Active low uncorrectable block indicator or no-signal
indicator. Mode selected by ERR_IND bit (#7) of the
QPSK_DIAG_CTL register (add. 0x67). Can also be
inverted.
O CMOS
Tri-state
Status output. Register defined function including I/O
audio frequency proportional to BER (acts as input
only in production test modes)
CMOS
5, 39, 55
27
7, 12, 44,
50, 59
17, 22,
32, 34
6, 8, 13,
40, 45 51,
54, 58
18, 21, 23
26, 28,
31, 33
Vdd
Vdd
CVdd
CVdd
Gnd
Gnd
Peripheral supply pins. All pins must be connected.
Peripheral supply pin used for the ADC.
Core supply pins. All pins must be connected.
PLL/ADC supply pins. All pins must be connected.
Ground supply pins. All pins must be connected.
PLL/ADC ground supply pins. All pins must be
connected.
Note 1: 5 V tolerant pins with thresholds related to 3.3 V.
V mA
3.3 2
3.3 2
3.3 12
3.3 2
3.3 2
3.3
3.3
1.8
1.8
0
0
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