Z90120 Datasheet PDF - Zilog.
| Part Number | Z90120 | |
| Description | 40-PIN LOW-COST DIGITAL TELEVISION CONTROLLER | |
| Manufacturers | Zilog. | |
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PRELIMINARY
Z90110/120/130
CP95TEL1300
PRELIMINARY
CUSTOMERPROCUREMENTSPECIFICATION
FEATURES
ROM
n Part (KB)
Z90110
4
Z90120
6
Z90130
8
*General-Purpose
RAM*
(Kbyte)
236
236
236
Speed
(MHz)
4
4
4
n 40-Pin DIP Package
n 4.5V to 5.5V Operating Range
n 0°C to +70°C Temperature Range
n Low-Power Consumption
Z90110/120/130
40-PINLOW-COSTDIGITAL
TELEVISIONCONTROLLER
n On-Screen Display (OSD) Logic Circuits
n One 14-Bit and Three 6-Bit Pulse Width Modulator
(PWM) Circuits
n 24 Input/Output Lines
n Program Memory, Video RAM, and Register File
Address Spaces
n Two On-Chip Counter/Timers
GENERAL DESCRIPTION
The Z901XX 40-pin Digital Television Controller is a cost-
effective member of the Z8® single-chip microcontroller
family. The device provides an ideal performance and
reliability solution for consumer and industrial television
applications.
The Z901XX offers mask-programmed ROM, which en-
ables the Z8 microcontroller to be used in a high-volume
production application device embedded with a custom
program (customer-supplied program) and combines to
provide support for mid-range and low-end TV applica-
tions.
The device features an 8-bit internal data path controlled
by a Z8 microcontroller, On-Screen Display (OSD) logic
circuits, and Pulse Width Modulators (PWM). On-chip
peripherals include two register mapped I/O ports (Ports 2
and Port 3), interrupt control logic (one software, two
external and three internal interrupts) and a standby mode
recovery input port (Port 3, pin P30).
The OSD control circuits support six rows by 20 columns
of characters. The character color is specified by row. One
of the eight rows is assigned to show two kinds of colors for
bar type displays such as volume control. The OSD is
capable of displaying either low resolution (5x7 dot pattern)
or high resolution (11x15 dot pattern) characters.
A 14-bit PWM port provides enough voltage resolution for
a voltage synthesizer tuning system. Three 6-bit PWM
ports are used for controlling audio signal levels, and
Three 8-bit PWM ports used to vary picture levels.
Three basic address spaces, The Program Memory, Video
RAM, and Register File, support a wide range of memory
configurations.
For applications demanding powerful I/O capabilities, the
Z901XX's dedicated input and output lines are grouped
into three ports, and are configurable under software
control to provide timing, status signals, parallel I/O and an
address/data bus for interfacing to external memory.
To unburden the program from coping with the real-time
problems such as counting/timing and data communication,
the Z901XX offers two on-chip counter/timers with a large
number of user selectable modes.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Power
Ground
Circuit
VCC
GND
Device
VDD
V
SS
CP95TEL1300 (10/95)
1
|
| |
 
PRELIMINARY
CAPACITANCE
TA=25°C;
V =GND=0V;
CC
Freq=1.0
MHz;
unmeasured
pins
to
GND.
Parameter
Input capacitance
Output capacitance
I/O capacitance
AFCIN input capacitance
Max Units
10 pF
20 pF
25 pF
10 pF
Z90110/120/130
CP95TEL1300
DC CHARACTERISTICS
TA=0°C to +70°C; VCC=+4.5V to +5.5V; FOSC=4 MHz
Sym Parameter
TA=0°C to +70°C Typical
Min Max @ 25°C Units Conditions
VIL Input Voltage Low
0
V Input XTAL/Osc In Low
ILC
V Input Voltage XTAL/Osc In High 0.7 V
IH CC
V Input XTAL/Osc In High
IHC
VHY Schmitt Hysteresis
V Maximum Pull-Up Voltage
PU
0.8 V
CC
0.1 VCC
VOL Output Voltage Low
V00-01
V
01-11
V
OH
AFC Level 01 In
AFC Level 11 In
Output Voltage High
I Reset Input Current
IR
I Input Leakage
IL
I Tri-State Leakage
OL
ICC Supply Current
ICC1
ICC2
Note:
[1] PWM open-drain
0.5 V
CC
V –0.4
CC
–3.0
–3.0
0.2 VCC
0.07 V
CC
V
CC
V
CC
12
0.4
0.4
0.45 VCC
0.75 V
CC
–80
3.0
3.0
20
6
10
1.48
0.98
3.2
3.0
0.8
0.16
0.19
1.9
3.12
4.75
–46
0.01
0.02
13.2
3.2
2.0
V
V External Clock Generator Driven
V External Clock Generator Driven
V External Clock Generator Driven
V
V [1]
V IOL=1.00 mA
V IOL=0.75 mA [1]
V
V
V I =–0.75 mA
OH
µA
V =0V
RL
µA
0V,V
CC
µA
0V,V
CC
mA All inputs at rail
mA All inputs at rail
µA All inputs at rail
5
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| Information | Total 8 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ Z90120.PDF Datasheet ] | |
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| Part Number | Description | MFRS |
| Z90120 | The function is 40-PIN LOW-COST DIGITAL TELEVISION CONTROLLER. Zilog. | |
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