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Z90102 Schematic ( PDF Datasheet ) - Zilog.

Teilenummer Z90102
Beschreibung 40-Pin Low-Cost Digital Television Controller
Hersteller Zilog.
Logo Zilog. Logo 




Gesamt 30 Seiten
Z90102 Datasheet, Funktion
PRODUCT SPECIFICATION
1
Z90102/103/104
40-PIN LOW-COST DIGITAL
TELEVISION CONTROLLER
1
FEATURES
8-Bit CMOS Microcontroller for Consumer
Television, Cable and Satellite Receiver Ap-
plications.
Device
ROM
(KB)
Z90102
Z90103
Z90104
4
6
8
Note: *General-Purpose
RAM*
(Bytes)
236
236
236
I/O
24
24
24
s Lowest Cost DTC Family Member
s Low Power Consumption
s Fast Instruction Pointer - 1.5 ms @ 4 MHz
s Two Standby Modes - STOP and HALT
s Low Voltage Detection/Voltage Sensitive Reset
s Port 2 (8-Bit Programmable I/O) and Port 3 (2-Bit Input,
3-Bit Output) Register Mapped Ports
s Port 6 (6-Bit Input and Tristate Comparator AFC Input)
Memory Mapped I/O Ports
s All Digital CMOS Levels Schmitt-Triggered
s Two Programmable 8-Bit Counter/Timers each with 6-
Bit Programmable Prescaler.
s Six Vectored, Priority Interrupts from Six Different
Sources
s Clock Speed up to 4 MHz
s On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC or External Clock Drive
s Permanently Enabled
Watch-Dog/Power-On Reset Timer
s 3K x 6-Bit Character Generator ROM
s 120 x 7-Bit Video RAM
s Mask Programmable 96-Character Set Display. The
90102 and 90103 6-Row x 20 Column Format, 12x15
Pixel Character Cell. The 90104 8-Row x 20 Column
Format 12x15 Pixel Character Cell. The 90102, 90103
90104 Capable of supporting English, Korean, Thai,
Chinese and Japanese High Resolution Characters.
s Fully Programmable Color Attributes Including Row
Character, Row Background/Fringes, Frame
Background/Position, Bar Graph Color Change, and
Character Size.
s Programmable Display Position and Character Size
Control
s One Pulse Width Modulator (14-Bit Resolution) for
Voltage Synthesis Tuner Control.
s Three Pulse Width Modulator (8-Bit Resolution) for
Picture Control
s Three Pulse Width Modulators (6-Bit Resolution) for
Audio Control
GENERAL DESCRIPTION
The Z90102/3/4 40-pin Low-Cost Digital Television Con-
troller are members of the Z8®STOP Mode MCU single-
chip family with 4, 6, and 8 KB of ROM and 236 bytes of
RAM. The device is offered in a 40-pin package and is
CMOS compatible. The DTC offers mask programmed
ROM which enables the Z8® MCU to be used in a high vol-
ume production application device embedded with a cus-
tom program (customer supplied program) and combines
DS97TEL1902
1






Z90102 Datasheet, Funktion
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
PIN DESCRIPTION
XTAL1, XTAL2. (time-based input, output, respectively).
These pins connect to the internal parallel-resonant clock
crystal (4 MHz max) oscillator circuit with two capacitors
to GND. XTAL1 is also used as an external clock input.
SCLK System Clock. SCLK is the internal system clock.
It can be used to clock external glue logic.
HSYNC (input, Schmitt triggered, CMOS level). Horizontal
Sync is an input pin that accepts an externally generated
Horizontal Sync signal of either negative or positive polar-
ity.
VSYNC (input,Schmitt-triggered, CMOS level). Vertical
Sync is an input pin that accepts an externally generated
Vertical Sync signal of either negative or positive polarity.
OSCIN, OSCOUT (Video Oscillator input, output, respec-
tively). Oscillator input and output pins for on-screen dis-
play circuits. These pins connect to an inductor and two
capacitors to generate the character dot clock (typically
around 6 MHz). The dot clock frequency determines the
character pixel width and phase synchronized to HSYNC.
Vblank Video Blank (output). CMOS output, programma-
ble polarity. Used as a superimpose control port to display
characters from video RAM. The signal controls Y signal
output of the CRT and turns off the incoming video display
while the characters in video RAM are superimposed on
the screen. The red, green, and blue outputs drive the
three electron guns on the CRT directly, while the blank
output turns off the Y signal.
Vblue Video Blue (output). CMOS Output of the Blue vid-
eo signal (B-Y) and is programmable for either polarity.
Vgreen Video Green (output). CMOS Output of the Green
video signal (G-Y) and is programmable for either polarity.
Vred Video Red (output). CMOS Output of the Red video
signal (R-Y) and is programmable for either polarity.
Port 2 (P27-P20). Port 2 is an 8-bit port, CMOS-compati-
ble, bit programmable for either input or output. Input buff-
ers are Schmitt triggered. Bits programmed as outputs
may be globally programmed as either push pull or open-
drain (Figure 9).
Zilog
Port 3 (P30, P31, P34-P36). Port 3, P30 input, is read di-
rectly. If appropriately enabled, a negative edge event is
latched in IRQ3 to initiate an IRQ3 vectored interrupt. An
application could place the device in STOP Mode when
P30 goes Low (in the IRQ3 interrupt routine). P30 initiates
a STOP Mode recovery when it subsequently goes to a
High. Port 3, P31 are read directly. If appropriately en-
abled, a negative edge event is latched in IRQ2 to initiate
an IRQ2 vectored interrupt. P31 High is signified as the
TIN signal to Timer1. Port 3, P34 and P35 are general-pur-
pose output lines. Port 3, P36 can be used as a general-
purpose output or as an output for TOUT (from Timer1 or
Timer2) or SCLK (Figure 10).
Port 6 (P65-P60). Port 6 is a 6-bit, Schmitt triggered
CMOS compatible, input port. The outputs of the AFC
comparators internally feed into the Port 6, bit 6 and bit 7
inputs (Figure 11).
AFCIN (Comparator input port, memory mapped). The in-
put signal is supplied to two comparators with VTH1=2/5
VCC and VTH2=3/5 VCC typical threshold voltage. The
comparator outputs are internally connected to Port 6, bit
6 and bit 7. AFCIN is typically used to detect AFC voltage
level to accommodate digital automatic fine tuning func-
tions (Figure 12).
Pulse Width Modulator 1 (PWM). PWM1 is typically used
as the D/A converter for Voltage Synthesis Tuning sys-
tems. It is a push-pull output with 14-bit resolution.
Pulse Width Modulator 6-8 (PWM). PWM8-PWM6 are
Pulse Width Modulators with 6-bit resolution.
Pulse Width Modulator 9, 10, 11 (PWM). Pulse Width
Modulator circuits with 8-bit resolution. These PWMs are
12 volt, open-drain outputs.
Pulse Width Modulator 1, 6, 7, 8 (PWM). Can be pro-
grammed as general-purpose outputs. PWM 1 is 5 VOH
push-pull, and PWMs 6, 7, 8 are 12 volt open-drain out-
puts.
/RESET System Reset. Code is executed from memory
address 000CH after the /RESET pin is set to a high level.
The reset function is also carried out by detecting a VCC
transition state (automatic Power-On Reset) so that the
external reset pin can be permanently tied to VCC. A low
level on /RESET forces a restart of the device.
6 DS97TEL1902

6 Page









Z90102 pdf, datenblatt
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
FUNCTIONAL DESCRIPTION
The Z8 DTCincorporates special functions to enhance the
Z8’s versatility in consumer, industrial and television con-
trol applications.
Pulse Width Modulator (PWM). The has seven PWM
channels (Figure 9). There are three types of PWM cir-
cuits: PWM1 (one channel of 14-bit resolution) typically
used for Voltage Synthesis Tuning, PWM8-PWM6 (three
channels of 6-bit resolution) typically used for audio level
control, and PWM9, 10, 11 (three channels of 8-bit resolu-
tion) typically used for picture level control. The PWM con-
trol registers are mapped into external memory and are ac-
cessed through LDE and LDEI instructions.
Zilog
PWM1. It is a push-pull output.
PWMs 6 through 11. They have their maximum values
(on times) when all 1s are loaded in their PWM Value reg-
isters (and minimum value for all 0s). PWM1 has a maxi-
mum value for all 0s and minimum value for all 1s.
On-Screen Display (OSD). The OSD has a capability of
displaying 6 rows x 20 columns of 96 kinds of characters
for high resolution (11 x 15 dots) patterns (Figures 10 and
11).
/RESET
XTAL
AD7-0
AD7-0
AD7-0
14-Bit Binary
Down Counter
14-Bit
PWM1
Reg
Upper 7-Bit
Lower 7-Bit
FC12-3h
13-0
6-Bit
PWM6
Reg
FC18h
FC19h
FC1Ah
5-0
6-0
13-7
13-7
6-0
5-0
5-0
8-Bit
PWM9
Reg
FC1Bh
FC1Ch
FC1Dh
7-0
7-0
7-0
7-Bit
Comparator
Pulse
Distributor
6-Bit
Comparator
8-Bit
Comparator
AD7-0
PWM Output
Port Reg
FC11h
7-0
AD7-0
PWM Mod Reg
FC10h
7-0
RS & DFF
0
PWM1 push-pull
output
RSFF
RSFF
RSFF
MPX
PWM6 (open-drain)
PWM7 (open-drain)
PWM8 (open-drain)
RSFF
RSFF
RSFF
PWM9 (open-drain)
PWM10 (open-drain)
PWM11 (open-drain)
Figure 9. Pulse Width Modulator Block Diagram
12 DS97TEL1902

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