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Z8019520FSC Schematic ( PDF Datasheet ) - Zilog.

Teilenummer Z8019520FSC
Beschreibung SMART PERIPHERAL CONTROLLERS
Hersteller Zilog.
Logo Zilog. Logo 




Gesamt 70 Seiten
Z8019520FSC Datasheet, Funktion
Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
PRELIMINARY PRODUCT SPECIFICATION
FEATURES
Part
Z80185
Z80195
ROM
(KB)
32 x 8
0
UART
Baud Rate
512 Kbps
512 Kbps
s 100-Pin QFP Package
s 5.0-Volt Operating Range
s Low-Power Consumption
s 0°C to +70°C Temperature Range
Speed
(MHz)
20, 33
20, 33
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
s Enhanced Z8S180 MPU
s Four Z80 CTC Channels
s One Channel ESCCController
s Two 8-Bit Parallel I/O Ports
s Bidirectional Centronics Interface (IEEE 1284)
s Low-EMI Option
GENERAL DESCRIPTION
The Z80185 and Z80195 are smart peripheral controller
devices designed for general data communications appli-
cations, and architected specifically to accommodate all
input and output (I/O) requirements for serial and parallel
connectivity. Combining a high-performance CPU core
with a variety of system and I/O resources, the Z80185/195
are useful in a broad range of applications. The Z80195 is
the ROMless version of the device.
The Z80185 and Z80195 feature an enhanced Z8S180
microprocessor linked with one enhanced channel of the
Z85230 ESCCserial communications controller, and 25
bits of parallel I/O, allowing software code compatibility
with existing software code.
Seventeen lines can be configured as bidirectional
Centronics (IEEE 1284) controllers. When configured as a
1284 controller, an I/O line can operate in either the host or
peripheral role in compatible, nibble, byte or ECP mode. In
addition, the Z80185 includes 32 Kbytes of on-chip ROM.
These devices are well-suited for external modems using
a parallel interface, protocol translators, and cost-effective
WAN adapters. The Z80185/195 is ideal for handling all
laser printer I/O, as well as the main processor in cost-
effective printer applications.
Notes:
All Signals with a preceding front slash, "/", are active Low.
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
V
CC
GND
V
DD
VSS
DS971850301
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Z8019520FSC Datasheet, Funktion
Zilog
TIMING DIAGRAMS
Z8S180 MPU Timing
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
Opcode Fetch Cycle
I/O Write Cycle †
I/O Read Cycle †
T1 T2 TW T3 T1 T2 TW T3 T1
5
4
23
ø
Address
1
6
/WAIT
20
19 19
20
11
7 12
/MREQ
/IORQ
/RD
/WR
/M1
8
9b
9a
10
14
18
7
28b
11
13 28a
29
13
9
22 25
26 and 26a
11
11
ST
Data
IN
Data
OUT
48
/RESET
54
17
15 16
15
23
24
49
48
54
53
Figure 4. CPU Timing
(Opcode Fetch Cycle, Memory Read/Write Cycle
I/O Read/Write Cycle)
16
21
27
49
53
6 DS971850301

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Z8019520FSC pdf, datenblatt
Zilog
PRELIMINARY
AC CHARACTERISTICS
V
DD
=
5V
±
10%,
V
SS
=
0V,
CL
=
50
pF
for
outputs
over
specified temperature range, unless otherwise noted.
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
No. Symbol Parameter
Z80185 / Z80195
(20 MHz)
Min Max
1 tcy
2 tCHW
3 tCLW
4 tcf
5 tcr
6 tAD
Clock Cycle Time
Clock “H” Pulse Width
Clock “L” Pulse Width
Clock Fall Time
Clock Rise Time
PHI Rising to Address Valid
50 (DC)
15
15
10
10
30
7 tAS
8 tMED1
9a tRDD1
9b tRDD1
10 tM1D1
11 tAH
12 tMED2
13 tRDD2
Address Valid to (MREQ Falling or IORQ Falling)
PHI Falling to MREQ Falling Delay
PHI Falling to RD Falling Delay (IOC=1)
PHI Rising to RD Falling Delay (IOC=0)
PHI Rising to M1 Falling Delay
Address Hold Time from (MREQ, IOREQ, RD, WR)
PHI Falling to MREQ Rising Delay
PHI Falling to RD Rising Delay
5
5
25
25
25
35
25
25
14 tM1D2
15 tDRS
16 tDRH
17 tSTD1
18 tSTD2
19 tWS
20 tWH
PHI Rising to M1 Rising Delay
Data Read Setup Time
Data Read Hold Time
PHI Falling to ST Falling Delay
PHI Falling to ST Rising Delay
WAIT Setup Time to PHI Falling
WAIT Hold Time from PHI Falling
40
10
0
30
30
15
10
21 tWDZ
22 tWRD1
23 tWDD
24 tWDS
25 tWRD2
26 tWRP
26a tWRP
27 WDH
PHI Rising to Data Float Display
PHI Rising to WR Falling Delay
PHI Rising to Write Data Delay Time
Write Data Setup Time to WR Falling
PHI Falling to WR Rising Delay
Write Pulse Width (Memory Write Cycle)
Write Pulse Width (I/O Write Cycle)
Write Data Hold Time From (WR Rising)
Notes:
Specifications 1 through 5 refer to an external clock input on EXTAL, and
provisionally to PHI clock output. When a quartz crystal is used with the
on-chip oscillator, a lower maximum frequency than that implied by spec.
#1 may apply.
35
25
25
10
25
75
130
10
Z80185 / Z80195
(33 MHz)
Min Max Units
33 (DC)
10
10
5
5
15
ns
ns
ns
ns
ns
ns
5
15
15
15
15
5
15
15
ns
ns
ns
ns
ns
ns
ns
ns
15
5
0
15
15
10
5
ns
ns
ns
ns
ns
ns
ns
20
15
15
10
15
45
70
5
ns
ns
ns
ns
ns
ns
ns
ns
12 DS971850301

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