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YSS902 Schematic ( PDF Datasheet ) - ETC

Teilenummer YSS902
Beschreibung Dolby Digital (AC-3) / Pro Logic decoder + Sub DSP
Hersteller ETC
Logo ETC Logo 




Gesamt 12 Seiten
YSS902 Datasheet, Funktion
YSS902
AC3D
Dolby Digital (AC-3) / Pro Logic decoder + Sub DSP
INTRODUCTION
The YSS902 is one chip LSI consisting of two built-in DSP’s ; Dolby Digital (AC-3) / Pro Logic (Main DSP) and a
sound processing DSP (Sub DSP). Sub DSP is capable of realizing various sound fields, such as virtual surround, by
down-loading the program and coefficient.
FEATURERS
Dolby Digital 5.1 channel full decode.
24 bit DSP. (Group-A Dolby Digital decoder)
No external memory is required. (Memory for center and surround channel delay is included)
Possible to decode multi-language encoded data. (possible to decode based on data-stream-number)
AC-3 karaoke mode.
Original compression mode as well as four compression modes recommended by Dolby.
Dolby Digital decoding latency is fixed to two audio blocks (512 samples).
Included de-emphasis filter.
Pro Logic decoding for Dolby Digital 2 channels decoded signal as well as ordinary PCM.
High performance 25 MIPS programmable DSP suitable for a variety of sound field processing such as original
surround, filtering, virtual surround etc.
Up to 1.36 second delay time is capable when used with an external 1Mbit SRAM. (at fs= 48 kHz)
Reads Dolby Digital decode information through the microprocessor interface.
Provide total sixteen I/O ports.
Possible to connect most of SPDIF receivers, A/D and D/A converters, by setting I/O data interface format.
Has a built-in PLL oscillation circuit to generates its own operating clock.
Internal operating clock is 25MHz.
Supply Voltage: 3.3v for core logic. 5v for I/Os.
Power saving mode.
Si-gate CMOS process.
100 QFP.(YSS902-F)
Note: "AC-3" and "Pro Logic" are registered trademarks of Dolby Laboratories Licensing Corporation.
Use of this LSI must be licensed by Dolby Laboratories Licensing Corporation.
YAMAHA CORPORATION
YSS902CATALOG
CATALOG No.:LSI-4SS902A3
1998. 7






YSS902 Datasheet, Funktion
YSS902
FUNCTION DESCRIPTION
The YSS902 consist of Main DSP section where AC-3/Pro Logic decoding is executed and Sub DSP section
where various sound field effects are added. Please refer to “BLOCK DIAGRAM” section.
Sub DSP is a 6 ch input / 6 ch output programmable DSP exclusively for the sound field processing. It can apply
such effects as virtual surround, echo and equalizing. In addition, with an SRAM up to 1Mbit connected, it can
produce reverberation for one second or longer. By using this function, it is possible to simulate various sound
fields such as a hall or a church.
* If adopting some technology owned by another company is desired for use in Sub DSP section, note that a
separate contract may be required between the owner of that technology and the user with respect to adoption of the
technology.
1. Clocks
XI, XO, CPO
The crystal oscillation circuit is formed by using XI and XO terminals. Oscillation frequency 50MHz is divided by
2 internally to provide the operating clock signals of 25MHz.
Clock signals should be obtained through self oscillation by using XI and XO terminals, or external clock signals
should be fed through the XI terminal.
This LSI operates in a PLL oscillation mode as well. When the PLL oscillation mode is selected and an external
clock signal whose frequency is lower than 49MHz is fed through the XI terminal and multiplied, connect an
external analog filter between CPO terminal and Ground.
2. Data Interface
SDIA0, SDIA1, SDOA0-2, SDIB0-2, SDOB0-2, SDWCK0, SDBCK0, SDWCK1,
SDBCK1, /SDBCK0
Main DSP section
AC-3 bitstream or PCM data should be fed from SDIA0 or SDIA1 terminal. These signals are processed by AC-3
/ Pro Logic decoding procedure in Main DSP section and then transmitted to Sub DSP section as well as
outputted through SDOA0-2 terminals.
Sub DSP section
In Sub DSP section, various types of processing can be applied to the PCM data decoded in Main DSP section or
inputted through SDIB0-2 terminals. Then, processed signals are outputted from each of SDOB0-2 terminals.
Following parameters can be selected by changing the control register setting.
. Selection of Main DSP input signal (SDIA0, SDIA1)
. Selection of Sub DSP input signal (Main DSP output, SDIB0-2 input)
. Polarity of bit clock and word clock
. Format and bit count of input/output data
For more information on the format of the input/output data, please refer to “Serial Data Interface” section.
3. Microprocessor Interface
/CS, /CSB, SCK, SI, SO
The control registers can be read/written via the serial microprocessor interface by using /CS, SCK, SI, and SO
terminals.
Please refer to the following format diagram for the details of read/write timing.
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YSS902 pdf, datenblatt
YSS902
IMPORTANT NOTICE
1. Yamaha reserves the right to make changes to its Products and to this document
without notice. The information contained in this document has been carefully checked
and is believed to be reliable. However, Yamaha assumes no responsibilities for
inaccuracies and makes no commitment to update or to keep current the information
contained in this document.
2. These Yamaha Products are designed only for commercial and normal industrial
applications, and are not suitable for other uses, such as medical life support equipment,
nuclear facilities, critical care equipment or any other application the failure of which could
lead to death, personal injury or environmental or property damage. Use of the Products
in any such application is at the customer's sole risk and expense.
3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL OR
SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR
IMPROPER USE OR OPERATION OF THE PRODUCTS.
4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS
ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR
ANYTHIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION
OF NON-INFRINGEMENT WITH RESPECT TO THE PRODUCTS. YAMAHA
SPECIFICALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD
PARTY ARISING FROM OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY
THIRD PARTY'S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT,
COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY.
5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE
CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA
ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR
OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE
EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH
RESPECT TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT
LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR USE AND TITLE.
Note) The specifications of this product are subject to improvement change without prior notice.
AGENCY
YAMAHA CORPORATION
Address inquiries to:
Semi-conductor Sales & Marketing Department
Head Office
203, Matsunokijima, Toyooka-mura,
Iwata-gun, Shizuoka-ken,438-0192
Tel. +81-539-62-4918 Fax. +81-539-62-5054
Tokyo Office 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568
Tel. +81-3-5488-5431 Fax. +81-3-5488-5088
Osaka Office
Nanba Tsujimoto Nissei Bldg. 4F
1-13-17, Nanba-naka, Naniwa-ku
Osaka City, Osaka, 556-0011
Tel. +81-6-633-3690 Fax. +81-6-633-3691
U.S.A Office YAMAHA Systems Technology.
100 Century Center Court, San Jose, CA 95112
Tel. +1-408-467-2300 Fax. +1-408-437-8791
COPYING PROHIBITED © 1987 YAMAHA CORPORATION Printed in Japan

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