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YGV619 Schematic ( PDF Datasheet ) - LSI Computer Systems

Teilenummer YGV619
Beschreibung Advanced Video Display Processor 6
Hersteller LSI Computer Systems
Logo LSI Computer Systems Logo 




Gesamt 15 Seiten
YGV619 Datasheet, Funktion
YGV619
AVDP6
Advanced Video Display Processor 6
s Outline
YGV619 is a VDP (Video Display Processor) adopting OSD display control system which is best suited to the
data broadcasting. The digital image interface of this device for connection with MPEG decoder has been
improved. The use of this device allows screen composition that is suited to mobile information terminals, car
navigation system, etc. Scan timing conforming to the display standard of digital TVs can be made.
Two built-in PLL circuits allows to realize superimposition of external image signal on original image signal,
and to produce clock best suited to SDRAM that is adopted as external video memory.
s Features
q Display planes: External digital image is overlaid with OSD images composed of regions.
Up to four planes, which are individually composed of back drop plane (plane on which external images are inputted)
+ region, are available.
q OSD image format:
8bit/dot palette mode, and 16 bit RGB or YCbCr format can be selected.
YCbCr conforms to the conversion method of ITU601.
Color palette (256 colors in 16777 k colors) can be specified by region.
q Digital image input format:
· 18bitR6G6B6
(Max. dot clock frequency: 80 MHz)
· 16bitYCbCr422 (Max. dot clock frequency: 80 MHz)
· 8bitITU656
(Dot clock frequency 27 MHz)
q Digital image output format:
· R6G6B6 + 2 bit AT
· 18bitYCbCr444 + 2 bit AT
· 16bitYCbCr422 + 2 bit AT
· 8bitITU656 + 2 bit AT + 6 bit α blending coefficient
q Max. OSD resolution: 960 dots × 1080 lines
(However, max. resolution of overlaid external image is 1920 ×1080 lines)
q Applicable digital TV image format:
· 525i
· 525p
· 1125i
q Video capture function:
· Draws external image input on the frame memory in real time.
· Can convert resolution.
· Provided with progressive scanning conversion
YGV619 CATALOG
CATALOG No.: LSI-4GV619A1
2001.01






YGV619 Datasheet, Funktion
YGV619
l DREQ (O)
DMA request. This pin is asserted when AVDP6 becomes a state where it can accept the DMA transfer. The DMA
transfer should be performed using regular WRn and RD pins. (Use Dual Address Mode of DMAC)
l RESET (I: Schmidt input)
Initial reset signal input. Inputting this signal clears the internal registers of AVDP6 to initialize the internal state of
the device. (Some registers are loaded with initial value.)
l LEND (I: Pull Up)
Selects an endian of CPU. Big endian is selected when this pin is at high level, or little endian when the level is low.
l SYCKS (I: Pull Up)
Input high level to this pin or leave it open (because it is provided with pull-up resister) when clock inputted through
DCKIN and DCKOUT pins are used as a system clock. VRAM clock and dot clock are generated from DCKIN. At this
time, supply of clock to SYCKIN pin is not needed. Input low level signal to this pin when input clock from SYCKIN and
SYCKOUT pins are used.
< SDRAM interface >
l SDQ31-0 (I/O)
Data bus for SDRAM. AVDP6 uses these pins for data input/out access to SDRAM. The data bus width for SDRAM
can be set to 32 bits or 16 bits by using the register setting. SDQ31-16 pins are not used when SDRAM bus width of 16
bits is used. At this time, SDQ31-16 pins are in output state at all times.
l SA12-0 (O)
Address bus for SDRAM. This bus uses time-sharing method to output row address and column address of SDRAM
used by AVDP6.
l SBA1-0 (O)
Outputs access bank of SDRAM and ACTIVE command at the same time.
SA12-0 and SBA1-0 pins output the signals as shown below depending on the type of SDRAM.
VRM SBA1 SBA0 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
0
- BA -
- BA -
- RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
- - - - CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
1
BA1 BA0
BA1 BA0
- RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
- - - - - CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
2
- BA RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
- BA - - - - - CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
3
- BA -
- BA -
- RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
- - - - CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
4
BA1 BA0
BA1 BA0
-
-
- RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
- - - - CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
5
BA1 BA0
BA1 BA0
- RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
- - - - - CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
6
- BA RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
- BA - - - - - CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
VRM shows the setting value of R#03:VRM[2:0]. Upper row shows the states of the pins when Active command is
issued, and lower column shows the state when Read/Write command is issued.
l SCS (O)
Outputs chip select signal for SDRAM. A command is issued to SDRAM when this signal is active. When two 16 bit
SDRAMs are used, connect this pin to both SDRAMs.
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YGV619 pdf, datenblatt
YGV619
s Example of System Configuration
AVDP6 is a display control device that operates as 16 bit or 32 bit I/O device on the external general purpose bus
of CPU on the system in which the device is built-in. Because CPU I/F of AVDP6 uses asynchronous I/F, it can be
controlled with general purpose SRAM I/F. SDRAM is connected on the local bus of AVDP6 to be used as video
memory. The timing for this SDRAM is made by AVDP6 independently. In the SDRAM, bit map image and palette
data that are displayed by AVDP6 are stored, and in addition, memory domain of SDRAM can be mapped directly
on the bus of CPU so that the vacant space is utilized as the work domain of CPU. The memory space of SDRAM is
controlled with general purpose SDRAM I/F.
Examples of system configuration are shown below by application.
Independent (free running) system
RAM ROM
CPU
dot clock
AVDP6
SDRAM
ITU601 8bit
YCbCr 16bit
RGB 18bit
RGB analog
When displaying bit map image stored in the video memory independently, it is possible to output sync
signal and display data that are compatible with various scan timing functions by supplying dot clock that is
suited to the display device and by writing timing parameter into the registers for internal scan timing. Since
the display data are outputted as analog and digital data, an LCD panel can be connected directly to the device
and video signal can be created by Video Encoder device.
OSD of NTSC digital images
RAM ROM
CPU
27MHz
MPEG2 ITU656
decoder
AVDP6
SDRAM
ITU656 NTSC
encoder
Video
This is an example of system configuration that uses AVDP6 to display OSD images of digital video
equipment conforming to NTSC (SDTV) such as DVD. Since AVDP6 is equipped with input / output pins for
digital images, the digital video signal can be inputted without converting it to analog signal, processed with
OSD and α blending without deteriorating the quality of images, and then outputted. When displaying bitmap
image of AVDP6 for external video with OSD, it is necessary to synchronize the external video signal with
scanning of AVDP6. At this time, OSD image can be synchronized with external video by inputting sync
signal of the external video into scan control circuit of AVDP6. (As the dot clock, use the clock that is
synchronized with external video signal.)
The digital image I/F of AVDP6 is compatible with digital I/F that conforms to CCIR-Rec601/656 (ITU656).
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