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PDF XR-T7295 Data sheet ( Hoja de datos )
| Número de pieza | XR-T7295 | |
| Descripción | DS3/Sonet STS-1 Integrated Line Receiver | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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...the analog plus companyTM
XR-T7295
DS3/Sonet STS-1
Integrated Line Receiver
FEATURES
D Fully Integrated Receive Interface for DS3 and
STS-1 Rate Signals
D Integrated Equalization (Optional) and Timing
Recovery
D Loss-of-Signal and Loss-of-Lock Alarms
D Variable Input Sensitivity Control
D 5V Power Supply
D Pin Compatible with XR-T7295E
D Companion Device to T7296 Transmitter
APPLICATIONS
D Interface to DS-3 Networks
D Digital Cross-Connect Systems
D CSU/DSU Equipment
D PCM Test Equipment
D Fiber Optic Terminals
June 1997-3
GENERAL DESCRIPTION
The XR-T7295 DS3/SONET STS-1 integrated line
receiver is a fully integrated receive interface that
terminates a bipolar DS3 (44.736Mbps) or Sonet STS-1
(51.84Mbps) signal transmitted over coaxial cable. (See
Figure 13).
The device also provides the functions of receive
equalization (optional), automatic-gain control (AGC),
clock-recovery and data retiming, loss-of-signal and
loss-of-frequency-lock detection. The digital system
interface is dual-rail, with received positive and negative
1s appearing as unipolar digital signals on separate
output leads. The on-chip equalizer is designed for cable
distances of 0 to 450ft. from the cross-connect frame to
the device. The receive input has a variable input
sensitivity control, providing three different sensitivity
settings, to adapt longer cables. High input sensitivity
allows for significant amounts of flat loss within the
system. Figure 1 shows the block diagram of the device.
The XR-T7295 device is manufactured using linear
CMOS technology. The XR-T7295 is available in either a
20-pin plastic DIP or 20-pin plastic SOJ package for
surface mounting.
Two versions of the chip are available, one is for either
DS3 or STS-1 operation (the XR-T7295, this data sheet),
and the other is for E3 operation (the XR-T7295E, refer to
the XR-T7295E data sheet). Both versions are pin
compatible.
For either DS3 or STS-1, an input reference clock at
44.736MHz or 51.84MHz provides the frequency
reference for the device.
ORDERING INFORMATION
Part No.
XR-T7295IP
XR-T7295IW
Package
20 Lead 300 Mil PDIP
20 Lead 300 Mil JEDEC SOJ
Operating
Temperature Range
-40°C to + 85°C
-40°C to + 85°C
Rev. 1.05
E1992
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
1
1 page  
XR-T7295
System A
ÎÎÎÎXR-T7296
ÎÎÎÎÎÎÎÎTransmitter
0-450 ft.
0-450 ft.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDSX-3
Cross
Connect
Frame
Î
or STSX-1
Type 728A
Coaxial Cable
System B
ÎÎÎÎÎXR-T7295
ÎÎÎÎÎÎÎÎÎÎReceiver
Figure 2. Application Diagram
SYSTEM DESCRIPTION
Receive Path Configurations
In the receive signal path (see Figure 1), the internal
equalizer can be included by setting REQB = 0 or
bypassed by setting REQB = 1. The equalizer bypass
option allows easy interfacing of the XR-T7295 device
into systems already containing external equalizers.
Figure 3 illustrates the receive path options.
In Case 1 of Figure 3, the signal from the DSX-3
cross-connect feeds directly into RIN. In this mode, the
user should set REQB = 0, engaging the equalizer in the
data path. Table 1 and the following sections describe the
receive signal requirements.
In Case 2 of Figure 3, external line build-out (LBO) and
equalizer networks precede the XR-T7295 device. In this
mode, the signal at RIN is already equalized, and the
on-chip filters should be bypassed by setting REQB=1.
The signal at RIN must meet the amplitude limits
described in Table 1
In applications where the XR-T7295 device is used to
monitor DS3 transmitter outputs directly, the receive
equalizer should be bypassed. Again, the signal at RIN
must meet the amplitude limits described in Table 1.
Minimum signals are for SOJ devices. Due to increased
package parasitics, add 3dB to all table values for DIP
devices.
Maximum input amplitude under all conditions is 850mV
pk.
Although system designers typically use power in dBm to
describe input levels, the XR-T7295 responds to peak
input signal amplitude. Therefore, the XR-T7295 input
signal limits are given in mV pk. Conversion factors are as
follows:
At DSX3: 390mV pk ' 0 dBm
At DSX3 + 450 ft. of cable: 310 mV pk ' 0 dBm
Data
Rate
DS3
STS-1
REQB
0
1
0
1
LOSTHR
0
VDD/2
VDD
0
VDD/2
VDD
0
VDD/2
VDD
0
VDD/2
VDD
Minimum
Signal
80
60
40
80
80
80
110
80
60
110
110
110
Unit
mV pk
mV pk
mV pk
mV pk
mV pk
mV pk
mV pk
mV pk
mV pk
mV pk
mV pK
mV pk
Table 1. Receive Input Signal Amplitude
Requirements
Rev. 1.05
5
5 Page 
XR-T7295
JITTER ACCOMMODATION
LOSS-OF-LOCK DETECTION
Under all allowable operating conditions, the jitter
accommodation of the XR-T7295 device exceeds all
system requirements for error-free operation
(BER<1E-9). The typical (VDD = 5V, T = 25°C, DSX-3
nominal signal level) jitter accommodation for the
XR-T7295 is shown in Figure 10.
FALSE-LOCK IMMUNITY
False-lock is defined as the condition where a PLL
recovered clock obtains stable phase-lock at a frequency
not equal to the incoming data rate. The XR-T7295
device uses a combination frequency/phase-lock
architecture to prevent false-lock. An on-chip frequency
comparator continuously compares the EXCLK reference
to the PLL clock. If the frequency difference between the
EXCLK and PLL clock exceeds approximately $0.5%,
correction circuitry forces re-acquisition of the proper
frequency and phase.
ACQUISITION TIME
If a valid input signal is assumed to be already present at
RIN, the maximum time between the application of device
power and error-free operation is 20ms. If power has
already been applied, the interval between the application
of valid data (or the action of valid data following a loss of
signal) and error-free operation is 4ms.
As stated above, the PLL acquisition aid circuitry monitors
the PLL clock frequency relative to the EXCLK frequency.
The RLOL alarm is activated if the difference between the
PLL clock and the EXCLK frequency exceeds
approximately $0.5%.
This will not occur until at least 250 bit periods after loss of
input data.
-----5432110ÎÎÎÎÎÎÎÎÎ100ÎÎÎÎÎÎÎÎÎ5ÎÎÎÎÎÎÎÎÎ0P0EÎÎÎÎÎÎÎÎÎ1AKKÎÎÎÎÎÎÎÎÎ= 0ÎÎÎÎÎÎÎÎÎ.055KdÎÎÎÎÎÎÎÎÎB1f30dKÎÎÎÎÎÎÎÎÎB =ÎÎÎÎÎÎÎÎÎ25005KÎÎÎÎÎÎÎÎÎk1H0z0ÎÎÎÎÎÎÎÎÎK ÎÎÎÎÎÎÎÎÎ500K
Frequency (Hz)
Figure 9. Typical PLL Jitter Transfer
Characteristic
411000..01ÎÎÎÎÎÎÎÎÎÎÎ1ÎÎÎÎÎÎÎÎÎÎÎG.8ÎÎÎÎÎÎÎÎÎÎÎ24 ÎÎÎÎÎÎÎÎÎÎÎ1ÎÎÎÎÎÎÎÎÎÎÎ0 ÎÎTÎÎÎÎÎÎÎÎÎRC-TaÎÎÎÎÎÎÎÎÎÎÎSteYg-PoÎÎ0ÎÎÎÎÎÎÎÎÎ1rU00y0B01T4ÎÎÎÎÎÎÎÎÎÎÎ59R49C-0TaÎÎ1ÎÎÎÎÎÎÎÎÎSte4Yg-o0ÎÎÎÎÎÎÎÎÎÎÎr0y0124K9ÎÎÎÎÎÎÎÎÎÎÎ9 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1ÎÎÎÎÎÎÎÎÎÎÎ0K ÎÎÎÎÎÎÎÎÎÎÎXÎÎÎÎÎÎÎÎÎÎÎR-T1ÎÎ7ÎÎÎÎÎÎÎÎÎ0209K5ÎÎÎÎÎÎÎÎÎÎÎTypÎÎÎÎÎÎÎÎÎÎÎicalÎÎÎÎÎÎÎÎÎÎÎ100ÎÎÎÎÎÎÎÎÎÎÎ0K
ÎÎÎÎÎÎÎÎXR-T7295 Typical
ÎÎÎÎÎÎÎÎJitter
ÎÎÎÎÎÎÎÎFrequency
(Hz)
Jitter
Amplitude
(U.I.)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5k
ÎÎÎÎÎÎÎÎ10k
60k
ÎÎÎÎÎÎÎÎ300k
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1M
10
5
1
0.5
0.4
Sinewave Jitter Frequency (Hz)
Figure 10. Input Jitter Tolerance at DSX-3 Level
Rev. 1.05
11
11 Page | ||
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| PDF Descargar | [ Datasheet XR-T7295.PDF ] | |
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