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XM28C020I-20 Schematic ( PDF Datasheet ) - Xicor Inc.

Teilenummer XM28C020I-20
Beschreibung 5 Volt/ Byte Alterable E2PROM
Hersteller Xicor Inc.
Logo Xicor Inc. Logo 




Gesamt 16 Seiten
XM28C020I-20 Datasheet, Funktion
XM28C020
2 Megabit Module
XM28C020
5 Volt, Byte Alterable E2PROM
256K x 8 Bit
TYPICAL FEATURES
High Density 2 Megabit (256K x 8) Module
Access Time of 150ns at –55°C to +125°C
Base Memory Component: Xicor X28C513
Pinout conforms to JEDEC Standard for
2 Megabit E2PROM
Fast Write Cycle Times
—128 Byte Page Write
—Byte or Page Write Cycle: 5ms Typical
—Complete Memory Rewrite: 10 Seconds
Early End of Write Detection
DATA Polling
—Toggle Bit Polling
Software Data Protection
Three Temperature Ranges
—Commercial: 0°C to +75°C
—Industrial: –40° to +85°C
—Military: –55° to +125°C
High Rel Module
—100% MIL-STD-883 Compliant Components
Endurance: 100,000 Cycles
FUNCTIONAL DIAGRAM
X28C513
A0–A15
I/O0–I/O7
OE
WE
CE
A0–A15
I/O0–I/O7
OE
WE
CE
A16
A17
X28C513
A0–A15
I/O0–I/O7
OE
WE
CE
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3872-1.9 6/18/97 T1/C0/D0 SH
DESCRIPTION
The XM28C020 is a high density 2 Megabit E2PROM
comprised of four X28C513 LCCs mounted on a co-fired
multilayered ceramic substrate. Individual components
are 100% tested prior to assembly in module form and
then 100% tested after assembly.
The XM28C020 is configured 256K x 8 bit. The module
supports a 128-byte page write operation. This com-
bined with DATA Polling or Toggle Bit Polling, effectively
provides a 39µs/byte write cycle, enabling the entire
array to be rewritten in 10 seconds.
The XM28C020 provides the same high endurance and
data retention as the X28C513.
X28C513
A0–A15
I/O0–I/O7
OE
WE
CE
X28C513
A0–A15
I/O0–I/O7
OE
WE
CE
PIN CONFIGURATION
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
XM28C020
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VCC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
3872 FHD F01
1
3872 FHD F02
Characteristics subject to change without notice






XM28C020I-20 Datasheet, Funktion
XM28C020
HARDWARE DATA PROTECTION
The XM28C020 provides three hardware features that
protect nonvolatile data from inadvertent writes.
• Noise Protection—A WE pulse less than 10ns will not
initiate a write cycle.
• Default VCC Sense—All functions are inhibited when
VCC is 3V.
• Write Inhibit—Holding OE LOW will prevent an inad-
vertent write cycle during power-up and power-down.
SOFTWARE DATA PROTECTION
The XM28C020 does provide the Software Data Protec-
tion (SDP) feature.
The module is shipped from Xicor with the Software
Data Protection NOT ENABLED; that is, the module will
be in the standard operating mode. In this mode, data
should be protected during power-up/-down operations
through the use of external circuits. The host system will
then have open read and write access of the module
once VCC is stable.
The module can be automatically protected during power-
up/-down without the need for external circuits by em-
ploying the SDP feature. The internal SDP circuit is
enabled after the first write operation utilizing the SDP
command sequence.
When this feature is employed, it will be easiest to
incorporate in the system software if the module is
viewed as a subsystem composed of four discrete
memory devices with an address decoder (see Func-
tional Diagram). In this manner, system memory map-
ping will extend onto the module. That is, the discrete
memory ICs and decoder should be considered memory
board components and SDP can be implemented at the
component level as described in the next section.
SOFTWARE COMMAND SEQUENCE
A16 and A17 are used by the decoder to select one of the
four LCCs. Therefore, only one of the four memory
devices can be accessed at one time. In order to protect
the entire module, the command sequence must be
issued separately to each device.
Enabling the software data protection mode requires the
host system to issue a series of three write operations:
each write operation must conform to the data and
address sequence illustrated in Figures 6 and 7.
Because this involves writing to a nonvolatile bit, the
device will become protected after tWC has elapsed.
After this point in time devices will inhibit inadvertent
write operations.
Once in the protected mode, authorized writes may be
performed by issuing the same command sequence that
enables SDP, immediately followed by the address/data
combination desired. The command sequence opens
the page write window enabling the host to write from
one to 128 bytes of data. Once the data has been
written, the device will automatically be returned to the
protected state.
In order to facilitate testing of the devices the SDP mode
can be deactivated. This is accomplished by issuing a
series of six write operations: each write operation must
conform to the data and address sequence illustrated in
Figures 8 and 9. This is a nonvolatile operation, and the
host will have to wait a minimum tWC before attempting
to write new data.
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XM28C020I-20 pdf, datenblatt
XM28C020
Write Cycle Limits
Symbol
tWC
tAS
tAH
tCS
tCH
tCW
tOES
tOEH
tWP
tWPH
tDV
tDS
tDH
tDW
tBLC
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
CE Pulse Width
OE High Setup Time
OE High Hold Time
WE Pulse Width
WE High Recovery
Data Valid
Data Setup
Data Hold
Delay to Next Write
Byte Load Cycle
WE Controlled Write Cycle
ADDRESS
CE
tAS
tCS
WE Controlled Write
Min.
Max.
10
0
125
25
0
125
10
10
100
100
1
50
10
10
0.3 100
CE Controlled Write (4)
Min.
Max.
10
0
125
0
25
100
10
35
125
100
1
50
35
10
0.3 100
tWC
tAH
tCH
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
3872 PGM T08.1
OE
WE
DATA IN
DATA OUT
tOES
tDV
tOEH
tWP
tWPH
DATA VALID
tDS
tDH
HIGH Z
3872 FHD F04
Note: (4) Due to the inclusion of the decoder IC on board the module the WE and CE write controlled timings will vary. When utilizing the
CE controlled write operation all the hold timings must be extended by the worst case propagation delay of the decoder. For a
WE controlled write operation CE must be a minimum 125ns to accommodate the additional setup time required.
12

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