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PDF IR2010SPBF Data sheet ( Hoja de datos )
| Número de pieza | IR2010SPBF | |
| Descripción | HIGH AND LOW SIDE DRIVER | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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Data Sheet No. PD60195-D
IR2010(S) & (PbF)
Features
HIGH AND LOW SIDE DRIVER
• Floating channel designed for bootstrap operation Product Summary
Fully operational to 200V
Tolerant to negative transient voltage, dV/dt immune
• Gate drive supply range from 10 to 20V
• Undervoltage lockout for both channels
• 3.3V logic compatible
VOFFSET
IO+/-
200V max.
3.0A / 3.0A typ.
Separate logic supply range from 3.3V to 20V
Logic and power ground ±5V offset
• CMOS Schmitt-triggered inputs with pull-down
• Shut down input turns off both channels
• Matched propagation delay for both channels
• Outputs in phase with inputs
• Also available LEAD-FREE
VOUT
ton/off
Delay Matching
10 - 20V
95 & 65 ns typ.
15 ns max.
Applications
• Audio Class D amplifiers
• High power DC-DC SMPS converters
• Other high frequency applications
Description
The IR2010 is a high power, high voltage, high speed power MOSFET and IGBT
drivers with independent high and low side referenced output channels, ideal for Audio
Class D and DC-DC converter applications. Logic inputs are compatible with standard
CMOS or LSTTL output, down to 3.0V logic. The output drivers feature a high pulse
current buffer stage designed for minimum driver cross-conduction. Propagation de-
lays are matched to simplify use in high frequency applications. The floating channel
can be used to drive an N-channel power MOSFET or IGBT in the high side configura-
tion which operates up to 200 volts. Proprietary HVIC and latch immune CMOS tech-
nologies enable ruggedized monolithic construction.
Packages
14-Lead PDIP
16-Lead SOIC
Typical Connection
200V
HO
VDD
VDD
VB
HIN HIN VS
SD SD
LIN LIN VCC
VSS VSS COM
VCC LO
(Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only.
Please refer to our Application Notes and DesignTips for proper circuit board layout.
www.irf.com
TO
LOAD
1
1 page  
HIN
LIN
SD
HO
LO
Figure 1. Input/Output Timing Diagram
IR2010(S) & (PbF)
HV =10 to 200V
<50 V/ns
Figure 2. Floating Supply Voltage Transient Test Circuit
(0 to 200V)
Figure 3. Switching Time Test Circuit
HIN
LIN
ton
HO
LO
50%
50%
tr
90%
toff tf
90%
10%
10%
Figure 4. Switching Time Waveform Definition
50%
SD
tsd
HO 90%
LO
Figure 5. Shutdown Waveform Definitions
www.irf.com
HIN 50%
LIN
50%
LO HO
10%
MT MT
90%
LO HO
Figure 6. Delay Matching Waveform Definitions
5
5 Page 
IR2010(S) & (PbF)
100 5.0
80 4.0
60 3.0
40
max
20
typ
0
2 4 6 8 10 12 14 16 18 20
VDD Voltage (V)
Figure 20B. Logic “1” Input Current vs. VDD Voltage
2.0
max
1.0
0.0
-50
-25
0
25 50 75 100 125
Temperature (C)
Figure 21A. Logic “0” Input Current vs. Temperature
5 .0 11.0
4 .0
3 .0
2 .0
m ax
1 .0
10.0
Max.
9.0
Typ.
8.0
Min.
7.0
0 .0
2 4 6 8 10 12 14 16 18 20
VDD Voltage (V)
Figure 21B. Logic “0” Input Current vs. VDD Voltage
6.0
-50
-25
0 25 50 75
Temperature (°C)
100 125
Figure 22. VBS Undervoltage (+) vs. Temperature
11.0 11.0
10.0
Max.
9.0
Typ.
8.0
7.0 Min.
10.0
Max.
9.0
Typ.
8.0
Min.
7.0
6.0
-50
-25
0 25 50 75
Temperature (°C)
100 125
Figure 23. VBS Undervoltage (-) vs. Temperature
www.irf.com
6.0
-50
-25
0 25 50 75
Temperature (°C)
100 125
Figure 24. VCC Undervoltage (+) vs. Temperature
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet IR2010SPBF.PDF ] | |
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