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SC14422 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer SC14422
Beschreibung Complete Baseband Processor for DECT Base Stations
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 7 Seiten
SC14422 Datasheet, Funktion
PRELIMINARY
March 1998
SC14422
Complete Baseband Processor for DECT Base Stations
General Description
Preliminary document version 1.1.
The SC14422 is a 3.0 Volt CMOS IC optimized to handle
all the audio, signal and data processing needed within a
DECT basestation. An ADPCM transcoder, a very low
power CODEC and Analog Frontend are integrated. Di-
rect connections towards analog or ISDN line interface.
The SC14422 is designed to be compatible with many
radio interfaces. A dedicated TDMA controller handles all
physical layer slot formats and radio control.
The integrated National Semiconductor’s standard
CR16A processor core with external Program memory
(Flash or ROM) takes care of all the higher protocol stack.
Programmable I/O ports can be configured as chip selects
for I/O expanders, Serial Flash memory, interrupt source
or I/O. A digital serial interface can be configured to inter-
face to many codecs and ISDN devices with µ-Law, a-Law,
linear or transparent data formats.
Features
s Integrated DECT base band transceiver optimized for
GAP base stations according to ETS 300 175-2, 175-3
& 175-8.
s 3.0 to 5.5 Volt operating voltage.
s Embedded 16 bit CompactRISCTM CR16A Microproc-
essor with In System Emulation (ISE) mode.
s 2k + 4kbyte Data Memory.
s Two full duplex 32 kbits/sec ADPCM transcoder.
s 14-bit linear CODEC with programmable gain
s Serial interface to external codecs and ISDN interface
circuits.
s Echo canceller, two echo suppressors, DTMF genera-
tor, sidetone and artificial echo loss.
s On-chip gaussian Modulator.
s Peak hold ADC for RSSI measurement
s Three input 8 bit successive approximation ADC.
s On board programmable Dedicated Instruction Proces-
sor (DIP) for all TDMA based events.
s Protected and unprotected half, full and double slot B-
fields D00, D08, D32 and D80
s Standard DECT encryption with different keys for
different MAC-connections.
s 6 MAC connections can be handled simultaneously.
s Flexible three wire interface to radio front synthesizer.
s Three general purpose I/O ports with programmable in-
terrupts.
s General purpose full duplex UART.
s SPITM and MICROWIRETM interfaces.
s Two general purpose timers and watchdog timer.
s Programmable chip selects to 8 bit wide ROM, SRAM
NAND Flash Memory and I/O expanders.
s Capture timer for frequency measurement for e.g. me-
tering, ringing and call progress tone detection.
s 100 pin TQFP-100 package.
________________________________________________________________________________________________
System Diagram
SC14401
SC14402
SC14422
ISDN or
PSTN
PSTN
Interface ISDN
SC14401
SC14402
SC14402
4220030
SPITM is a trademark of Motorola, MICROWIRETM and CompactRISCTM are trademarks of National Semiconductor Corporation
Copyright 1998 National Semiconductor Corp.
1
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SC14422 Datasheet, Funktion
Table 1: Pin Description)
PIN NAME
RSTn
HOLDn
or MI
NR TYPE
68 1
69 2
ACSn
AD3..0
DAB7..0
RCSn
AD10
RDn
AD11
AD9
AD8
AD13
AD14
AD17
WRn
AD16,15, 12
AD7-4
CLK1M
70
71-74
82-75
83
84
85
86
87
88
89
90
91
92
93-95
96-99
100
5
1
1
5
1
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
INPUT. Active low Reset.
INPUT/OUTPUT with fixed pull up. Selects HOLD mode. If set to ‘0’, the CR16A
processor will terminate its current instruction and the ADx, WRN, RDN will go TRI-
STATE. In this mode an external CR16A can control the SC14422 completely.
In Emulation mode MI output is automatically selected. Then this pin goes high if
an internal interrupt is asserted. In core mode this pin is a maskable interrupt input
MI to the CR16A core.
OUTPUT. Auxiliary Chip Select not. This signal becomes low if the address range
is within the programmed address range.
OUTPUT. Address bit 3 to 0. In HOLD mode these pins are input.
INPUT/OUTPUT. Data bus bit 7..0
OUTPUT. ROM Chip Select not. Low active if none of the internal peripherals or the
ACSn is addressed.
OUTPUT. Address bit 10. In HOLD mode this pin is input.
OUTPUT. Active low read. In HOLD mode this pin is input.
OUTPUT. Address bit 11. In HOLD mode this pin is input.
OUTPUT. Address bit 9. In HOLD mode this pin is input.
OUTPUT. Address bit 8. In HOLD mode this pin is input.
OUTPUT. Address bit 13. In HOLD mode this pin is input.
OUTPUT. Address bit 14. In HOLD mode this pin is input.
OUTPUT. Address bit 17. In HOLD mode this pin is output.
OUTPUT. Active low write signal. In HOLD mode this pin is input.
OUTPUT. Address bit 16,15 & 12. In HOLD mode these pins are input.
OUTPUT. Address bit 7 to 4. In HOLD mode these pins are input.
OUTPUT. Fixed bit clock output (1.152Mhz). Synchronized to the DECT bit clock.
Will be logic ‘0’ if the DECT Dedicated Instruction Processor (DIP) is frozen.
Will be logic ‘1’ after a hardware reset (RSTN) or software reset (DEBUG_REG[1]).
NOTE: All digital outputs can sink/source 2 mA unless otherwise specified. All digital inputs are Schmitt trigger
types. After reset all I/Os are set to input and all pull-up or pull-down resistors are enabled. The p0[0] pull-
up resistor is disabled at start-up.
Copyright 1998 National Semiconductor Corp.
6
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