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K9F2808U0C-DCB0 Schematic ( PDF Datasheet ) - Samsung semiconductor

Teilenummer K9F2808U0C-DCB0
Beschreibung 16M x 8 Bit / 8M x 16 Bit NAND Flash Memory
Hersteller Samsung semiconductor
Logo Samsung semiconductor Logo 




Gesamt 33 Seiten
K9F2808U0C-DCB0 Datasheet, Funktion
K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-VCB0,VIB0
K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0
FLASH MEMORY
Document Title
16M x 8 Bit , 8M x 16 Bit NAND Flash Memory
Revision History
Revision No. History
0.0 Initial issue.
1.0 TBGA PKG Dimension Change
48-Ball, 6.0mm x 8.5mm --> 63-Ball, 9.0mm x 11.0mm
2.0 1.A3 Pin assignment of TBGA Package is changed.(Page 4)
(before) NC --> (after) Vss
2. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 32)
3. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 33)
2.1 The min. Vcc value 1.8V devices is changed.
K9F28XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V
Draft Date
Apr. 15th 2002
Sep. 5th 2002
Dec.10th 2002
Mar. 6th 2003
Pb-free Package is added.
2.2
K9F2808U0C-FCB0,FIB0
K9F2808Q0C-HCB0,HIB0
K9F2816U0C-HCB0,HIB0
K9F2816U0C-PCB0,PIB0
K9F2816Q0C-HCB0,HIB0
K9F2808U0C-HCB0,HIB0
K9F2808U0C-PCB0,PIB0
Mar. 13rd 2003
Some AC parameter is changed(K9F28XXQ0C).
2.3
tWC tWH tWP tRC tREH tRP tREA tCEA
Before 45 15 25 50 15 25 30 45
After 60 20 40 60 20 40 40 55
Mar. 26th 2003
2.4 New definition of the number of invalid blocks is added.
May. 24th 2003
(Minimum 502 valid blocks are guaranteed for each contiguous 64Mb
memory space)
Remark
Advance
Advance
Preliminary
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1






K9F2808U0C-DCB0 Datasheet, Funktion
K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-VCB0,VIB0
K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0
FLASH MEMORY
PIN DESCRIPTION
Pin Name
I/O0 ~ I/O7
(K9F2808X0C)
I/O0 ~ I/O15
(K9F2816X0C)
Pin Function
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The
I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.
COMMAND LATCH ENABLE
CLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
ALE The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
CE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase opertion. Regarding CE control during read
operation, refer to ’Page read’section of Device operation .
READ ENABLE
RE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
WE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
WP The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
R/B
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
VccQ
OUTPUT BUFFER POWER
VCCQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
Vcc
POWER
VCC is the power supply for device.
Vss GROUND
N.C
NO CONNECTION
Lead is not internally connected.
GND
GND INPUT FOR ENABLING SPARE AREA
To do sequential read mode including spare area , connect this input pin to Vss or set to static low state
or to do sequential read mode excluding spare area , connect this input pin to Vcc or set to static high state.
DNU
DO NOT USE
Leave it disconnected.
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
6

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K9F2808U0C-DCB0 pdf, datenblatt
K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-VCB0,VIB0
K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0
FLASH MEMORY
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
K9F2808Q0C
Min Max
K9F2808U0C
Min Max
CLE Set-up Time
tCLS
0
-
0
-
CLE Hold Time
tCLH
10
-
10
-
CE Setup Time
tCS 0 - 0 -
CE Hold Time
tCH 10 - 10 -
WE Pulse Width
tWP 40 - 25 -
ALE Setup Time
tALS
0
-
0
-
ALE Hold Time
tALH
10
-
10
-
Data Setup Time
tDS 20 - 20 -
Data Hold Time
tDH 10 - 10 -
Write Cycle Time
tWC 60 - 45 -
WE High Hold Time tWH 20 - 15 -
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE :
1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
Parameter
Symbol
Data Transfer from Cell to Register
ALE to RE Delay
CLE to RE Delay
Ready to RE Low
RE Pulse Width
WE High to Busy
Read Cycle Time
CE Access Time
RE Access Time
RE High to Output Hi-Z
CE High to Output Hi-Z
RE or CE High to Output hold
RE High Hold Time
Output Hi-Z to RE Low
WE High to RE Low
Device Resetting Time(Read/Program/Erase)
Last RE High to Busy
(at sequential read)
K9F2808U0C-
Y,P,V,F only
CE High to Ready(in case of inter-
ception by CE at read)
CE High Hold Time(at the last
serial read)(2)
tR
tAR
tCLR
tRR
tRP
tWB
tRC
tCEA
tREA
tRHZ
tCHZ
tOH
tREH
tIR
tWHR
tRST
tRB
tCRY
tCEH
K9F2808Q0C
Min Max
- 10
10 -
10 -
20 -
40 -
- 100
60 -
- 55
- 40
- 30
- 20
15 -
20 -
0-
60 -
- 5/10/500(1)
- 100
- 50 +tr(R/B)(3)
100 -
K9F2808U0C
Min Max
- 10
10 -
10 -
20 -
25 -
- 100
50 -
- 45
- 30
- 30
- 20
15 -
15 -
0-
60 -
- 5/10/500(1)
- 100
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
- 50 +tr(R/B)(3) ns
100 - ns
NOTE :
1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
12

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