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PDF K9F1G08Q0A Data sheet ( Hoja de datos )
| Número de pieza | K9F1G08Q0A | |
| Descripción | FLASH MEMORY | |
| Fabricantes | Samsung semiconductor | |
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K9F1G08Q0A
K9F1G08U0A
Document Title
128M x 8 Bit NAND Flash Memory
Revision History
Revision No History
0.0 1. Initial issue
0.1 1. The tADL(Address to Data Loading Time) is added.
- tADL Minimum 100ns (Page 11, 23~26)
- tADL is the time from the WE rising edge of final address cycle
to the WE rising edge of first data cycle at program operation.
2. Added Addressing method for program operation
0.2 1. Add the Protrusion/Burr value in WSOP1 PKG Diagram.
0.3 1. PKG(TSOP1, WSOP1) Dimension Change
FLASH MEMORY
Draft Date Remark
Aug. 24. 2003 Advance
Jan. 27. 2004 Preliminary
Apr. 23. 2004 Preliminary
May. 19. 2004
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
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K9F1G08Q0A
K9F1G08U0A
FLASH MEMORY
PIN DESCRIPTION
Pin Name
I/O0 ~ I/O7
Pin Function
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
COMMAND LATCH ENABLE
CLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
ALE The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
CE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode.
READ ENABLE
RE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
WE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
WP The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
R/B
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
Vcc
POWER
VCC is the power supply for device.
Vss GROUND
N.C
NO CONNECTION
Lead is not internally connected.
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
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K9F1G08Q0A
K9F1G08U0A
FLASH MEMORY
Program / Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
tPROG
-
300 700
µs
Dummy Busy Time for Cache Program
tCBSY
3 700 µs
Number of Partial Program Cycles
in the Same Page
Main Array
Spare Array
Nop
-
-
-
-
4 cycles
4 cycles
Block Erase Time
tBERS
-
2
3 ms
NOTE : 1. Max. time of tCBSY depends on timing between internal program completion and data in
AC Timing Characteristics for Command / Address / Data Input
Parameter
CLE setup Time
CLE Hold Time
CE setup Time
CE Hold Time
WE Pulse Width
ALE setup Time
ALE Hold Time
Data setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
ALE to Data Loading Time
Symbol
tCLS
tCLH
tCS
tCH
tWP
tALS
tALH
tDS
tDH
tWC
tWH
tADL
Min
K9F1G08Q0A
K9F1G08U0A
25 10
10 5
35 15
10 5
25 15
25 10
10 5
20 10
10 5
45 30
15 10
100(1)
100(1)
Max
K9F1G08Q0A
K9F1G08U0A
--
--
--
--
--
--
--
--
--
--
--
--
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet K9F1G08Q0A.PDF ] | |
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