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K9F1208Q0B Schematic ( PDF Datasheet ) - Samsung semiconductor

Teilenummer K9F1208Q0B
Beschreibung 64M x 8 Bit NAND Flash Memory
Hersteller Samsung semiconductor
Logo Samsung semiconductor Logo 




Gesamt 30 Seiten
K9F1208Q0B Datasheet, Funktion
ELECTRONICS
March. 2003
San 16 Banwol-Ri
Taean-Eup Hwasung- City
Kyungki Do, Korea
Tel.) 82 - 31 - 208 - 6463
Fax.) 82 - 31 -208 - 6799
512Mb/256Mb 1.8V NAND Flash Errata
Description : Some of AC characteristics are not meeting the specification.
> AC characteristics : Refer to Table
Affected Products : K9F1208Q0A-XXB0, K9F1216Q0A-XXB0
K9F5608Q0C-XXB0, K9F5616Q0C-XXB0
K9K1208Q0C-XXB0, K9K1216Q0C-XXB0
Improvement schedule : The components without this restriction will
be available from work week 23 or after.
Workaround : Relax the relevant timing parameters according to the table.
Table
UNIT : ns
Parameters
tWC tWH tWP tRC tREH tRP tREA tCEA
Specification
45 15 25 50 15 25 30 45
Relaxed Condition 80 20 60 80 20 60 60 75
Sincerely,
Product Planning & Application Eng.
Memory Division
Samsung Electronics Co.
1






K9F1208Q0B Datasheet, Funktion
K9F1208U0A-VCB0,VIB0,FCB0,FIB0
K9F1208Q0A-DCB0,DIB0,HCB0,HIB0
K9F1208U0A-YCB0,YIB0,PCB0,PIB0
K9F1208U0A-DCB0,DIB0,HCB0,HIB0
K9F1216Q0A-DCB0,DIB0,HCB0,HIB0
K9F1216U0A-YCB0,YIB0,PCB0,PIB0
K9F1216U0A-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
63-Ball TBGA (measured in millimeters)
Top View
8.50±0.10
#A1
(Datum A)
Bottom View
#A1 INDEX MARK(OPTIONAL)
8.50±0.10
0.80 x 9= 7.20
0.80 x 5= 4.00
0.80
654321
A
B
A
B
(Datum B) C
D
E
F
G
H
63-0.45±0.05
0.20 M A B
0.10MAX
Side View
15.00±0.10
2.00
0.45±0.05
5

6 Page









K9F1208Q0B pdf, datenblatt
K9F1208U0A-VCB0,VIB0,FCB0,FIB0
K9F1208Q0A-DCB0,DIB0,HCB0,HIB0
K9F1208U0A-YCB0,YIB0,PCB0,PIB0
K9F1208U0A-DCB0,DIB0,HCB0,HIB0
K9F1216Q0A-DCB0,DIB0,HCB0,HIB0
K9F1216U0A-YCB0,YIB0,PCB0,PIB0
K9F1216U0A-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
Memory Map
The device is arranged in four 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte(X8 device) or 264 word(X16
device) page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from
each plane. The block address map is configured so that multi-plane program/erase operations can be executed for every four
sequential blocks.
Figure 3. Memory Array Map
Plane 0
(1024 Block)
Block 0
Page 0
Page 1
Page 30
Page 31
Block 4
Page 0
Page 1
Page 30
Page 31
Plane 1
(1024 Block)
Block 1
Page 0
Page 1
Page 30
Page 31
Block 5
Page 0
Page 1
Page 30
Page 31
Plane 2
(1024 Block)
Block 2
Page 0
Page 1
Page 30
Page 31
Block 6
Page 0
Page 1
Page 30
Page 31
Plane 3
(1024 Block)
Block 3
Page 0
Page 1
Page 30
Page 31
Block 7
Page 0
Page 1
Page 30
Page 31
Block 4088
Page 0
Page 1
Page 30
Page 31
Block 4092
Page 0
Page 1
Page 30
Page 31
Block 4089
Page 0
Page 1
Page 30
Page 31
Block 4093
Page 0
Page 1
Page 30
Page 31
528byte Page Registers
528byte Page Registers
Block 4090
Page 0
Page 1
Page 30
Page 31
Block 4094
Page 0
Page 1
Page 30
Page 31
528byte Page Registers
Block 4091
Page 0
Page 1
Page 30
Page 31
Block 4095
Page 0
Page 1
Page 30
Page 31
528byte Page Registers
11

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