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K7A801801M Schematic ( PDF Datasheet ) - Samsung semiconductor

Teilenummer K7A801801M
Beschreibung 256Kx36 & 512Kx18 Synchronous SRAM
Hersteller Samsung semiconductor
Logo Samsung semiconductor Logo 




Gesamt 18 Seiten
K7A801801M Datasheet, Funktion
K7A803609B
K7A801809B
256Kx36 & 512Kx18 Synchronous SRAM
Document Title
256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No.
0.0
0.1
0.2
0.3
1.0
2.0
2.1
3.0
History
Initial draft
1. Delete pass- through
1. Add x32 org part and industrial temperature part
1. change scan order(1) form 4T to 6T at 119BGA(x18)
1. Final spec release
2. Change ISB2 form 50mA to 60mA
Remove tCYC 225MHz(-22)
1. Delete 119BGA package
1. Remove x32 organization
2. Remove -20 speed bin
Draft Date
Remark
May. 18 . 2001 Preliminary
June. 26. 2001 Preliminary
Aug. 11. 2001 Preliminary
Aug. 28. 2001 Preliminary
Nov. 16. 2001 Final
April. 01. 2002 Final
April. 04. 2003 Final
Nov. 17. 2003 Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - Nov. 2003
Rev 3.0






K7A801801M Datasheet, Funktion
K7A803609B
K7A801809B
256Kx36 & 512Kx18 Synchronous SRAM
FUNCTION DESCRIPTION
The K7A803609B and K7A801809B are synchronous SRAM designed to support the burst address accessing sequence of the
Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and
duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS1.
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7
and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initi-
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
LBO PIN
HIGH
First Address
Fourth Address
Case 1
A1 A0
00
01
10
11
Case 2
A1 A0
01
00
11
10
TABLE
LBO PIN
LOW
First Address
Fourth Address
Case 1
A1 A0
00
01
10
11
Case 2
A1 A0
01
10
11
00
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
Case 3
A1 A0
10
11
00
01
Case 3
A1 A0
10
11
00
01
(Interleaved Burst)
Case 4
A1 A0
11
10
01
00
(Linear Burst)
Case 4
A1 A0
11
00
01
10
ASYNCHRONOUS TRUTH TABLE
OPERATION
Sleep Mode
Read
Write
Deselected
ZZ OE I/O STATUS
HX
High-Z
LL
DQ
LH
High-Z
L X Din, High-Z
LX
High-Z
Notes
1. X means "Dont Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
- 6 - Nov. 2003
Rev 3.0

6 Page









K7A801801M pdf, datenblatt
K7A803609B
K7A801809B
256Kx36 & 512Kx18 Synchronous SRAM
- 12 -
Nov. 2003
Rev 3.0

12 Page





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