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K6R1008C1A-I12 Schematic ( PDF Datasheet ) - Samsung semiconductor

Teilenummer K6R1008C1A-I12
Beschreibung 128Kx8 High Speed Static RAM5V Operating/ Revolutionary Pin out. Operated at Commercial and Industrial Temperature Ranges.
Hersteller Samsung semiconductor
Logo Samsung semiconductor Logo 




Gesamt 8 Seiten
K6R1008C1A-I12 Datasheet, Funktion
PRELIMINARY
K6R1008C1A-C, K6R1008C1A-I
CMOS SRAM
Document Title
128Kx8 High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev. No.
Rev. 0.0
Rev. 1.0
Rev. 2.0
Rev. 3.0
Rev. 4.0
History
Initial release with Preliminary.
Release to final Data Sheet.
1.1. Delete Preliminary
Update D.C parameters.
2.1. Update D.C parameters
ITEMS
Previous spec.
(12/15/17/20ns part)
ICC 200/190/180/170mA
ISB 30mA
ISB1 10mA
Updated spec.
(12/15/17/20ns part)
170/165/165/160mA
25mA
8mA
Add Industrial Temperature Range parts and 300mil-SOJ PKG.
3.1. Add 32-Pin 300mil-SOJ Package.
3.2. Add Industrial Temperature Range parts with the same parame-
ters as Commercial Temperature Range parts.
3.2.1. Add K6R1008C1A parts for Industrial Temperature Range.
3.2.2. Add ordering information.
3.2.3. Add the condition for operating at Industrial Temp. Range.
3.3. Add the test condition for VOH1 with VCC=5V±5% at 25°C
3.4. Add timing diagram to define tWP as ″(Timing Wave Form of
Write Cycle(CS=Controlled)
4.1. Delete 17ns Part
Draft Data
Apr. 22th, 1995
Feb. 29th, 1996
Remark
Preliminary
Final
Jul. 16th, 1996
Final
Jun. 2nd, 1997
Final
Feb. 25th, 1998 Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 4.0
February 1998






K6R1008C1A-I12 Datasheet, Funktion
PRELIMINARY
K6R1008C1A-C, K6R1008C1A-I
CMOS SRAM
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
Address
OE
CS
WE
Data in
Data out
tWC
tAW
tCW(3)
tWR(5)
tAS(4)
tWP(2)
High-Z
tOHZ(6)
tDW tDH
Valid Data
High-Z(8)
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
Address
CS
WE
Data in
Data out
tAS(4)
High-Z
tWC
tAW
tCW(3)
tWP1(2)
tWR(5)
tWHZ(6)
tDW tDH
Valid Data
High-Z(8)
tOW (10) (9)
-6-
Rev 4.0
February 1998

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