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K6E0808C1C-C Schematic ( PDF Datasheet ) - Samsung semiconductor

Teilenummer K6E0808C1C-C
Beschreibung 32Kx8 Bit High Speed CMOS Static RAM
Hersteller Samsung semiconductor
Logo Samsung semiconductor Logo 




Gesamt 8 Seiten
K6E0808C1C-C Datasheet, Funktion
K6E0808C1C-C
PRELIMINARY
CMOS SRAM
Document Title
32Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out.
Revision History
RevNo. History
Rev. 0.0 Initial release with Preliminary.
Rev. 1.0
Release to final Data Sheet.
1. Delete Preliminary
Rev. 2.0
Update A.C parameters
2.1. Updated A.C parameters
Items
Previous spec.
(12/15/20ns part)
Updated spec.
(12/15/20ns part)
tOE
- / 8/10ns
- / 7 /9 ns
tCW
- /12/ - ns
- /11/ - ns
tHZ
8/10/10ns
6/ 7/10ns
tOHZ
- / 8 / - ns
- / 7 / - ns
tDW
- / 9 / - ns
- / 8 / - ns
2.2. Add VOH1=3.95V with the test condition as Vcc=5V±5% at 25°C
Rev. 3.0
3.1. Add 28-TSOP1 Package.
3.2. Add L-version.
3.3. Add Data Rentention Characteristics.
Rev. 4.0
4.1. Delete DIP Package.
4.2. Delete L-version.
4.3. Delete Data Retention Characteristics and Waveform.
Draft Data
Apr. 1st, 1994
May 14th,1994
Remark
Preliminary
Final
Oct. 4th, 1994
Final
Feb. 22th, 1996 Final
Feb. 25th, 1998 Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 4.0
February 1998






K6E0808C1C-C Datasheet, Funktion
PRELIMINARY
K6E0808C1C-C
CMOS SRAM
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL
levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
Address
OE
CS
WE
Data in
Data out
tWC
tAW
tCW(3)
tWR(5)
tAS(4)
tWP(2)
High-Z
tOHZ(6)
tDW tDH
Valid Data
High-Z(8)
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
Address
CS
WE
Data in
Data out
tAS(4)
High-Z
tWC
tAW
tCW(3)
tWP1(2)
tWR(5)
tWHZ(6)
tDW tDH
Valid Data
High-Z(8)
tOW (10) (9)
-6-
Rev 4.0
February 1998

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