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S524C20D10 Schematic ( PDF Datasheet ) - Samsung semiconductor

Teilenummer S524C20D10
Beschreibung 1K/2K/4K/8K-bit Serial EEPROM with software write protect
Hersteller Samsung semiconductor
Logo Samsung semiconductor Logo 




Gesamt 22 Seiten
S524C20D10 Datasheet, Funktion
S524C20D10/20D20/80D40/80D80
1K/2K/4K/8K-bit
Serial EEPROM
with software write protect
Data Sheet
OVERVIEW
The S524C20D10/20D20/80D40/80D80 serial EEPROM has a 1,024/2,048/4,096/8,192-bit (128/256/512/1,024-
byte) capacity, supporting the standard I2C™-bus serial interface. It is fabricated using Samsungs’ most
advanced CMOS technology. Important features are a hardware-based write protection circuit for the entire
memory area and software-based write protection logic for the lower 128 bytes. Hardware-based write protection
is controlled by the state of the write-protect (WP) pin. The software-based method is one-time programmable
and permanent. Using one-page write mode, you can load up to 16 bytes of data into the EEPROM in a single
write operation. Another significant feature of the S524C20D10/20D20/80D40/80D80 is its support for fast mode
and standard mode.
FEATURES
I2C-Bus Interface
Two-wire serial interface
Automatic word address increment
EEPROM
1K/2K/4K/8K-bit (128/256/512/1,024-byte)
storage area
16-byte page buffer
Typical 3.5 ms write cycle time with
auto-erase function
Hardware-based write protection for the entire
EEPROM (using the WP pin)
Software-based write protection for the lower
128-byte EEPROM
EEPROM programming voltage generated
on chip
1,000,000 erase/write cycles
100 years data retention
Operating Characteristics
Operating voltage
— 2.5 V to 5.5 V (write)
— 2.2 V to 5.5 V (read)
Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200 µA at 5.5 V
— Maximum stand-by current: < 5 µA at 3.3 V
Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
Electrostatic discharge (ESD)
— 3,000 V (HBM)
— 300 V (MM)
Packages
8-pin DIP, SOP, and TSSOP
4-1






S524C20D10 Datasheet, Funktion
S524C20D10/20D20/80D40/80D80 SERIAL EEPROM
DATA SHEET
I2C-BUS PROTOCOLS
Here are several rules for I2C-bus transfers:
— A new data transfer can be initiated only when the bus is currently not busy.
— MSB is always transferred first in transmitting data.
— During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is High.
The I2C-bus interface supports the following communication protocols:
Bus not busy: The SDA and the SCL lines remain High level when the bus is not active.
Start condition: Start condition is initiated by a High-to-Low transition of the SDA line while SCL remains High
level. All bus commands must be preceded by a start condition.
Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains
High level. All bus operations must be completed by a stop condition (see Figure 4-7).
SCL
SDA
Start
Condition
Data or Data
ACK Valid Change
Stop
Condition
Figure 4-7. Data Transmission Sequence
Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration
of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock
pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total
number of bytes that can be transferred in one operation is theoretically unlimited.
ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter
(the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master
generates, the receiver pulls the SDA line low to acknowledge that it successfully received the eight bits of
data (see Figure 4-8). But the slave does not send an ACK if an internal write cycle is still in progress.
In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors
the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to
transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition
to be issued by the master before returning to its stand-by mode.
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S524C20D10 pdf, datenblatt
S524C20D10/20D20/80D40/80D80 SERIAL EEPROM
DATA SHEET
CURRENT ADDRESS BYTE READ OPERATION
The internal word address pointer maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either read or write) was to the address “n”, the next read operation would access
data at address “n+1”.
When the S524C20D10/20D20/80D40/80D80 receives a slave address with the R/W bit set to “1”, it issues an
ACK and sends the eight bits of data. The master does not acknowledge the transfer but it does generate a Stop
condition. In this way, the S524C20D10/20D20/80D40/80D80 effectively stops the transmission (see Figure 4-
13).
Start Slave Address
Data
Stop
AN
CO
K
A
C
K
Figure 4-13. Current Address Byte Read Operation
4-12

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