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IP1202 Schematic ( PDF Datasheet ) - International Rectifier

Teilenummer IP1202
Beschreibung Dual Output Full Function 2 Phase Synchronous Buck Power Block Integrated Power Semiconductors/ PWM Control & Passives
Hersteller International Rectifier
Logo International Rectifier Logo 




Gesamt 29 Seiten
IP1202 Datasheet, Funktion
PD-94593C
iP1202
Features
• 5.5V to 13.2V input voltage
• 0.8V to 5V output voltage
• 2 Phase Synchronous Buck Power Block
• 180° out of phase operation
• Single or Dual output capability
• Dual 15A maximum load capability
• Single 2 phase 30A maximum load capability
• 200-400kHz per channel nominal switching frequency
• Over Current Hiccup or Over Current Latch
• External Synchronization Capable
• Overvoltage protection
• Individual soft start per outputs
• Over Temperature protection
• Internal features minimize layout sensitivity *
• Ease of layout
• Very small outline 15.5mm x 9.25mm x 2.6mm
Description
Dual Output Full Function 2 Phase
Synchronous Buck Power Block
Integrated Power Semiconductors,
PWM Control & Passives
iP1202 Power Block
The iP1202 is a fully optimized solution for medium current synchronous buck applications requiring up to 15A
or 30A. The iP1202 is optimized for 2 phase single output applications up to 30A or dual output, each up to
15A with interleaved input. It includes full function PWM control, with optimized power semiconductor chip-sets
and associated passives, achieving high power density. Very few external components are required to create
a complete synchronous buck power supply.
iPOWIR technology offers designers an innovative space-saving solution for applications requiring high power
densities. iPOWIR technology eases design for applications where component integration offers benefits in
performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat
transfer and component selection.
iP1202 Configurations
Channel 1
V IN
V OUT
V IN
V OUT
Channel 2
V OUT
Single Output
Dual Output
* Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques
should be applied for the design of the power supply board. The iPOWIR block will function normally, but not optimally without any additional input decoupling
capacitors. Input decoupling capacitors should be added at Vin pin for stable and reliable long term operation. See layout guidelines in datasheet for more
detailed information.
www.irf.com
10/28/04
1






IP1202 Datasheet, Funktion
iP1202
1.060
2.0
1.045
1.030
1.015
1.000
VOU T 1 =VOU T 2 =1.5V
IOU T 1 =IOU T 2 =15A
f S W =300k Hz
L =1.0µ H
T B L K =125°C
1.5
1.0
0.5
0.0
0.985
- 0.5
0.970
- 1.0
0.955
- 1.5
0.940
- 2.0
0.925
- 2.5
5 6 7 8 9 10 11 12 13 14
Input Voltage (V)
Fig. 4: Normalized Power Loss vs. VIN
1.060
1.045
1.030
1.015
1.000
VI N =12V
VOU T 1 =VOU T 2 =1.5V
IOU T 1 =I OU T 2 =15A
L =1.0µ H
T B L K =125°C
0.985
0.970
0.955
0.940
0.925
0.910
200
250 300 350
Sw itching Fre que ncy (k Hz)
2.0
1.5
1.0
0.5
0.0
- 0.5
- 1.0
- 1.5
- 2.0
- 2.5
- 3.0
400
Fig. 6: Normalized Power Loss vs. Frequency
55
50 VOUT = 1.5V
45 fsw = 300kHz
40
35
L = 1.0µH
TBLK = 125°C
205
185
165
145
125
30
25
Vin = 12V
105
85
20
15
Vin = 5.5V
65
45
10 25
55
6 8 10 12 14 16 18 20 22 24
Overload Current (A)
Fig. 8: Nominal Overcurrent Threshold Setting
External Resistor Selection
6
1.120
1.105
1.0 9 0
1.0 7 5
1.0 6 0
VI N =12V
IOU T 1 =I OU T 2 =15A
f SW =300kHz
L =1.0µ H
T B L K =125°C
4.0
3.5
3.0
2.5
2.0
1.0 4 5
1.5
1.0 3 0
1.0
1.0 15
0.5
1.0 0 0
0.0
0.985
- 0.5
0.970
- 1.0
0.955
- 1.5
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Output V oltage (V )
Fig. 5: Normalized Power Loss vs. VOUT
1.24
1.21
1.18
1.15
1.12
VI N =12V
VOU T 1 =VOU T 2 =1.5V
IOU T 1 =IOU T 2 =15A
f SW =300kHz
T B L K =125°C
8.0
7.0
6.0
5.0
4.0
1.09 3.0
1.06 2.0
1.03 1.0
1.00 0.0
0.97 - 1.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6
Output Inductance (PH)
Fig. 7: Normalized Power Loss vs. Inductance
400
380
360
340
320
300
280
260
240
220
200
20 25 30 35 40 45 50
RT in kOhms
Fig. 9: Per Channel Switching Frequency vs RT
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IP1202 pdf, datenblatt
iP1202
iP1202 User’s Design Guidelines
The iP1202 can be configured as a dual channel 15A
or parallel single 30A power block consisting of opti-
mized power semiconductors, PWM control and its
associated passive components. It is based on a syn-
chronous buck topology and offers an optimized so-
lution where space, efficiency and noise caused by
parasitics are of concern. The phase shifted, two out-
put power block operates with fixed frequency volt-
age mode control and can be configured to operate
as a dual output or paralleled single output with cur-
rent sharing. The iP1202 components are integrated
in a ball grid array (BGA) package.
VIN
The input operating voltage range of the iP1202 is
5.5V to 13.2V. Both channels of the power block have
a common input.
Enabling the Outputs
The ENABLE pin turns on and turns off both outputs
of the iP1202 simultaneously. The iP1202 outputs will
be turned off by floating the ENABLE pin. ENABLE
low will start the outputs. The converter can also be
shutdown by pulling the soft-start pins to PGND
through a logic level MOSFET the drain of which con-
nects to the soft start pin (see Fig.12). This feature
can be useful if sequencing or different start-up tim-
ing of the outputs are required. In situations where
the output has undergone a latched shutdown due to
overvoltage or overcurrent, cycling ENABLE will re-
set the outputs. Cycling soft start pins will not unlatch
the outputs.
Dual Soft Start
The Soft Start function provides a controlled rise of
the output voltage, thus limiting the inrush current
during start-up. The iP1202 provides two indepen-
dent soft start functions. The soft start pins can be
connected to the soft start capacitors to provide dif-
ferent start-up and sequencing profiles.
Each soft start function has an internal 25uA +/-20%
current source that charges the external soft start
capacitor Css up to 3V. During power-up, the output
voltage starts ramping up only after the charging
voltage across the Css capacitor has reached a
0.8Vtyp threshold, as shown in Fig. 13.
This threshold voltage should be taken into consid-
eration when designing sequencing profiles using
the iP1202 as it will effect start-up delays and ramp-
times.
For proper implementation of sequencing of outputs
using the iP1202, refer to IR Application Note AN-
1053 - Power sequencing techniques using iP1201
and iP1202.
Iss
SS1/SS2 iP1202
Css
Fig. 12: Soft Start/Enable Circuit
3V
0.8Vtyp
VCss
VOUT
Fig. 13: Power Up Threshold
Mode of Operation
The iP1202 can be configured to provide either two
independent dual outputs or single paralleled output
with current share. In dual output mode, the two error
amplifiers of the PWM controller operate indepen-
dently. Each output voltage of the iP1202 block is
controlled by its own error amplifier. The output of
the error amplifier and the internally generated ramp
signal are compared to produce PWM pulses of fixed
frequency that drive the internal power switches. In
this mode, the VP-ref pin must be connected to Vref
pin. Vref pin is the internally generated 0.8V refer-
ence input of first error amplifier . Refer to the inter-
nal block diagram of the iP1202 in Fig.1.
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