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PDF ITF86130SK8T Data sheet ( Hoja de datos )

Número de pieza ITF86130SK8T
Descripción 14A/ 30V/ 0.0078 Ohm/ N-Channel/ Logic Level/ Power MOSFET
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! ITF86130SK8T Hoja de datos, Descripción, Manual

TM
Data Sheet
14A, 30V, 0.0078 Ohm, N-Channel, Logic
Level, Power MOSFET
Packaging
SO8 (JEDEC MS-012AA)
BRANDING DASH
1
2
3
4
Symbol
SOURCE(1)
SOURCE(2)
5
DRAIN(8)
DRAIN(7)
SOURCE(3)
GATE(4)
DRAIN(6)
DRAIN(5)
ITF86130SK8T
June 2000 File Number 4798.4
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.0078Ω, VGS = 10V
- rDS(ON) = 0.010Ω, VGS = 4.5V
- rDS(ON) = 0.012Ω, VGS = 4.0V
• Gate to Source Protection Diode
• Simulation Models
- Temperature Compensated PSPICE™ and SABER
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.intersil.com
• Peak Current vs Pulse Width Curve
• Transient Thermal Impedance Curve vs Board Mounting
Area
• Switching Time vs RGS Curves
Ordering Information
PART NUMBER
PACKAGE
BRAND
ITF86130SK8T
SO8
86130
NOTE: When ordering, use the entire part number. ITF86130SK8T
is available only in tape and reel.
Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified
ITF86130SK8T
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous
Continuous
(TA=
(TA=
25oC,
25oC,
VGS
VGS
=
=
10V) (Figure 2) (Note 2)
4.5V) (Note 2) . . . . . . . .
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ID
ID
Continuous
Continuous
(TA=
(TA=
100oC,
100oC,
VGS
VGS
=
=
4.5V)
4.0V)
(Note
(Note
2)
2)
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ID
ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Power Dissipation (Note 2)
Derate Above 25oC . . . .
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PD
...
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Tech brief TB370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
NOTES:
1. TJ = 25oC to 125oC.
2. 50oC/W measured using FR-4 board with 0.76in2 (490.3mm2) copper pad at 10s.
30
30
±20
14.0
12.0
7.0
7.0
Figure 4
2.5
20
-55 to 150
300
260
V
V
V
A
A
A
A
A
W
mW/oC
oC
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000

1 page




ITF86130SK8T pdf
ITF86130SK8T
Typical Performance Curves (Continued)
1.2
ID = 250µA
1.1
1.0
5000
COSS CDS + CGD
1000
CISS = CGS + CGD
0.9
-80
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
VGS = 0V, f = 1MHz
200
0.1 1.0
CRSS = CGD
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10
VDD = 15V
8
6
4
WAVEFORMS IN
2 DESCENDING ORDER:
ID = 12A
ID = 2A
0
0 10 20 30 40 50 60
Qg, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
400
VGS = 4.5V, VDD = 15V, ID = 7.0A
300
tr
200
tf
td(OFF)
100
td(ON)
0
0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE ()
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
400
VGS = 10V, VDD = 15V, ID = 14A
td(OFF)
300
tf
200
tr
100
td(ON)
0
0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE ()
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
5

5 Page





ITF86130SK8T arduino
ITF86130SK8T
MS-012AA
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE
EA
E1 A1
e
D
b
h x 45o
c
L
0.060
1.52
0o- 8o
0.004 IN
0.10 mm
0.050
1.27
0.155
4.0
0.275
7.0
0.024
0.6
MINIMUM RECOMMENDED FOOTPRINT FOR
SURFACE-MOUNTED APPLICATIONS
1.5mm
DIA. HOLE
MS-012AA
12mm TAPE AND REEL
12mm
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.0532 0.0688 1.35
1.75
-
A1
0.004
0.0098 0.10
0.25
b
0.013
0.020
0.33
0.51
-
-
c
0.0075 0.0098 0.19
0.25
-
D
0.189
0.1968 4.80
5.00
2
E
0.2284 0.244
5.80
6.20
-
E1 0.1497 0.1574 3.80 4.00
e 0.050 BSC
1.27 BSC
3
-
H
0.0099 0.0196 0.25
0.50
-
L
0.016
0.050
0.40
1.27
4
NOTES:
1. All dimensions are within allowable dimensions of Rev. C of
JEDEC MS-012AA outline dated 5-90.
2. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.006 inches (0.15mm) per side.
3. Dimension “E1” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 0.010 inches
(0.25mm) per side.
4. “L” is the length of terminal for soldering.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. Controlling dimension: Millimeter.
7. Revision 8 dated 5-99.
4.0mm
USER DIRECTION OF FEED
2.0mm
1.75mm
CL
COVER TAPE
8.0mm
40mm MIN.
ACCESS HOLE
18.4mm
330mm
13mm
50mm
GENERAL INFORMATION
1. 2500 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.
11
12.4mm

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