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PDF ISL6563 Data sheet ( Hoja de datos )
| Número de pieza | ISL6563 | |
| Descripción | Two-Phase Multi-Phase Buck PWM Controller with Integrated MOSFET Drivers | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
December 2003
ISL6563
FN9126.2
Two-Phase Multi-Phase Buck PWM
Controller with Integrated MOSFET
Drivers
The ISL6563 two-phase PWM control IC provides a
precision voltage regulation system for advanced
microprocessors. Multi-phase power conversion is a marked
departure from single phase converter configurations
employed to satisfy the increasing current demands of
modern microprocessors and other electronic circuits. By
distributing the power and load current, implementation of
multi-phase converters utilize smaller and lower cost
transistors with fewer input and output capacitors. These
reductions accrue from the higher effective conversion
frequency with higher frequency ripple current due to the
phase interleaving process of this topology.
Outstanding features of this controller IC include
programmable VID codes compatible with Intel VRM9,
VRM10, as well as AMD’s Hammer microprocessors, along
with a system regulation accuracy of ±1%. The droop
characteristic, used to reduce the overshoot or undershoot
of the output voltage, is easily programmed with a single
resistor.
Important features of this controller IC include a set of
sophisticated over-voltage and over-current protection.
Over-voltage results in the converter turning the lower
MOSFETs ON to clamp the rising output voltage and protect
the microprocessor. Like other Intersil multiphase
controllers, the ISL6563 uses cost and space-saving
rDS(ON) sensing for channel current balance, dynamic
voltage positioning, and over-current protection. Channel
current balancing is automatic and accurate with the
integrated current-balance control system. Over-current
protection can be tailored to any application with no need for
additional parts. These features provide advanced protection
for the microprocessor and power system.
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE PKG. DWG. #
ISL6563CR-T
0 to 70 24 Ld 4x4 QFN L24.4x4B
ISL6563IR-T
0 to 70 24 Ld 4x4 QFN L24.4x4B
ISL6563EVAL1 Evaluation Platform
Features
• Integrated Two-Phase Power Conversion
• Both 5V and 12V Conversion
• Precision Channel Current Sharing
- Loss-Less Current Sampling - Uses rDS(ON)
• Precision Output Voltage Regulation
- ±1% System Accuracy Over Temperature (Commercial)
• Microprocessor Voltage Identification Inputs
- Up to a 6-Bit DAC
- Selectable between Intel’s VRM9, VRM10, or AMD’s
Hammer DAC codes
- Resistor-Programmable Droop Voltage
• Fast Transient Recovery Time
• Over-Current Protection
• Improved, Multi-tiered Over-Voltage Protection
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Pinout
ISL6563 (QFN)
TOP VIEW
24 23 22 21 20 19
VID1 1
18 PHASE1
VID0 2
17 LGATE1
DACSEL/VID5 3
VRM10 4
25
GND
16 PVCC
15 LGATE2
COMP 5
14 PGND
FB 6
13 PHASE2
7 8 9 10 11 12
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6563
Electrical Specifications Test Conditions: VCC = 5V, TJ = 0oC to 85oC, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN TYP
OVER-CURRENT PROTECTION
Over-Current Trip Level
- 95
PROTECTION
Over-Voltage Threshold while IC Disabled
VRM9.0 configuration
1.90 1.95
Hammer and VRM10.0 configurations
1.60 1.65
Over-Voltage Threshold
FB Rising
- VID
+200mV
Over-Voltage Hysteresis
- 100
SWITCHING TIME
UGATE Rise Time (Note 3)
LGATE Rise Time (Note 3)
UGATE Fall Time (Note 3)
LGATE Fall Time (Note 3)
UGATE Turn-On Non-overlap (Note 3)
LGATE Turn-On Non-overlap (Note 3)
OUTPUT
tRUGATE; VVCC = 5V, 3nF Load
tRLGATE; VVCC = 5V, 3nF Load
tFUGATE; VVCC = 5V, 3nF Load
tFLGATE; VVCC = 5V, 3nF Load
tPDHUGATE; VVCC = 5V, 3nF Load
tPDHLGATE; VVCC = 5V, 3nF Load
-8
-8
-8
-4
-8
-8
Upper Drive Source Resistance
100mA Source Current
- 0.5
Upper Drive Sink Resistance
100mA Sink Current
- 0.4
Lower Drive Source Resistance
100mA Source Current
0.5
Lower Drive Sink Resistance
100mA Sink Current
- 0.3
NOTE:
3. Parameter magnitude guaranteed by design.
MAX UNITS
- µA
2.00 V
1.70 V
-V
- mV
- ns
- ns
- ns
- ns
- ns
- ns
1.3 Ω
1.0 Ω
1.3 Ω
1.0 Ω
Timing Diagram
tPDHUGATE
tRUGATE
tFUGATE
UGATE
LGATE
tFLGATE
tPDHLGATE
tRLGATE
Functional Pin Description
VCC (Pin 8)
Bias supply for the IC’s small-signal circuitry. Connect this
pin to a 5V supply and locally decouple using a quality 0.1µF
ceramic capacitor.
5
PVCC (Pin 16)
Power supply pin for the MOSFET drives. Connect this pin to
a 5V supply and locally decouple using a quality 1µF
ceramic capacitor.
GND and PGND (Pins 25 and 14)
Connect these pins to the circuit ground using the shortest
possible paths. All internal small-signal circuitry is
referenced to the GND pin. LGATE drive is referenced to the
PGND pin.
5 Page 
ISL6563
TABLE 3. VRM10 VOLTAGE IDENTIFICATION CODES
VID4
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID2
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID1
1
1
1
0\
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID5
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VDAC
Off
Off
0.8375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
1.0500
1.0625
1.0750
1.0875
1.1000
1.1125
1.1250
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.300
1.3125
1.3250
1.3375
1.3500
1.3625
TABLE 3. VRM10 VOLTAGE IDENTIFICATION CODES
(Continued)
VID4 VID3 VID2 VID1 VID0 VID5 VDAC
1 0 0 1 1 1 1.3750
1 0 0 1 1 0 1.3875
1 0 0 1 0 1 1.4000
1 0 0 1 0 0 1.4125
1 0 0 0 1 1 1.4250
1 0 0 0 1 0 1.4375
1 0 0 0 0 1 1.4500
1 0 0 0 0 0 1.4625
0 1 1 1 1 1 1.4750
0 1 1 1 1 0 1.4875
0 1 1 1 0 1 1.5000
0 1 1 1 0 0 1.5125
0 1 1 0 1 1 1.5250
0 1 1 0 1 0 1.5375
0 1 1 0 0 1 1.5500
0 1 1 0 0 0 1.5625
0 1 0 1 1 1 1.5750
0 1 0 1 1 0 1.5875
0 1 0 1 0 1 1.6000
DYNAMIC VID (VID-ON-THE-FLY)
The ISL6563 is capable of executing on-the-fly output
voltage changes. The way the ISL6563 reacts to a change in
the VID code is dependent on the VID configuration. In
VRM9 or AMD Hammer settings, the ISL6563 checks for a
change in the VID code four times each switching cycle. The
VID code is the bit pattern present at pins VID4-VID0. If a
new code is established and it stays the same for 3
consecutive readings, the ISL6563 begins changing the
reference by making one step change every four switching
cycles until the it reaches the new VID code. Figure 5
depicts such a transition, from 1.5V to 1.7V
01110
00110
VVID
VID CHANGE OCCURS HERE
1.5V
VREF (100mV/div)
1.5V
VOUT (100mV/div)
FIGURE 5. TYPICAL DYNAMIC-VID OPERATION, VRM9 DAC
SETTING
11
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| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ISL6563.PDF ] | |
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