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PDF IDT7099S Data sheet ( Hoja de datos )
| Número de pieza | IDT7099S | |
| Descripción | HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Integrated Device Technology, Inc.
HIGH-SPEED
4K x 9 SYNCHRONOUS
DUAL-PORT RAM
IDT7099S
FEATURES:
• High-speed clock-to-data output times
— Military: 20/25/30ns (max.)
— Commercial: 15/20/25ns (max.)
• Low-power operation
— IDT7099S
Active: 900 mW (typ.)
Standby: 50 mW (typ.)
• Architecture based on Dual-Port RAM cells
— Allows full simultaneous access from both ports
— Independent bit/byte Read and Write inputs for control
functions
• Synchronous operation
— 4ns setup to clock, 1ns hold on all control, data, and
address inputs
— Data input, address, and control registers
— Fast 15ns clock to data out
— 20ns cycle times, 50MHz operation
• Clock enable feature
• Guaranteed data output hold times
• Available in 68-pin PGA, 68-pin PLCC, and 80-pin TQFP
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT7099 is a high-speed 4K x 9 bit synchronous Dual-
Port RAM. The memory array is based on Dual-Port memory
cells to allow simultaneous access from both ports. Registers
on control, data, and address inputs provide low set-up and
hold times. The timing latitude provided by this approach
allow systems to be designed with very short realized cycle
times. With an input data register, this device has been
optimized for applications having unidirectional data flow or
bi-directional data flow in bursts. Changing data direction from
reading to writing normally requires one dead cycle.
These Dual-Ports typically operate on only 900mW of
power at maximum high-speed clock-to-data output times as
fast as 15ns. An automatic power down feature, controlled
by CE, permits the on-chip circuitry of each port to enter a very
low standby power mode.
The IDT7099 is packaged in a 68-pin PGA, 68-pin PLCC,
and a 80-pin TQFP. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
I/O8L
I/O0-7L
WRITE
LOGIC
MMYAAREERMRMRAOOAYRRYY
WRITE
LOGIC
SENSE
SENSE
AMPS DECODER DECODER AMPS
I/O8R
I/O0-7R
BIT OEL
BYTE OEL
CLKL
CLKEN
REG
en
REG
en
WBIT R/ L
WBYTE R/ L
CEL
REG
Write
Control
Logic
A0L-A11L A0R-A11R
Write
Control
Logic
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.23
REG
BIT OER
BYTE OER
CLKR
CLKENR
WBIT R/ R
WBYTE R/ R
CER
3007 drw 01
OCTOBER 1996
DSC-3007/3
1
1 page  
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATAOUT
347Ω
5V
893Ω
30pF
3007 drw 05
Figure 1. AC Output Test load.
DATAOUT
347Ω
5V
893Ω
5pF
3007 drw 06
Figure 2. Output Test Load
(For tCLZ, tCHZ, tOLZ, and tOHZ).
Including scope and jig.
∆tCD
(Typical, ns)
8
7
6
5
4
3
2
1
- 10pF is the I/O capacitance
of this device, and 3pF is the
AC Test Load Capacitance
0
20 40 60 80 100 120 140 160 180 200
-1 Capacitance (pF)
3007 drw 07
Figure 3. Typical Output Derating (Lumped Capacitive Load).
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE RANGE —
(READ AND WRITE CYCLE TIMING)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = -55°C to +125°C)
Commercial
Military
7099S15 7099S20 7099S25 7099S20 7099S25 7099S30
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCYC
Clock Cycle Time
20 — 20 —
25 — 20 — 25 — 30 — ns
tCH Clock High Time
6— 8 —
10 — 8 — 10 — 12 — ns
tCL Clock Low Time
6— 8 —
10 — 8 — 10 — 12 — ns
tCD Clock High to Output Valid
— 15 — 20
— 25 — 20 — 25 — 30 ns
tS Registered Signal Set-up Time
4— 5 —
6 — 5 — 6 — 7 — ns
tH Registered Signal Hold Time
1— 1 —
1 — 2 — 2 — 2 — ns
tDC Data Output Hold After Clock High 3 — 3 —
3 — 3 — 3 — 3 — ns
tCKLZ Clock High to Output Low-Z(1,2)
2— 2 —
2 — 2 — 2 — 2 — ns
tCKHZ Clock High to Output High-Z(1,2)
—7 — 9
— 12 — 9 — 12 — 15 ns
tOE Output Enable to Output Valid
— 8 — 10
— 12 — 10 — 12 — 15 ns
tOLZ Output Enable to Output Low-Z(1,2)
0— 0 —
0 — 0 — 0 — 0 — ns
tOHZ Output Disable to Output High-Z(1,2) — 7 — 9
— 11 — 9 — 11 — 14 ns
tSCK Clock Enable, Disable Set-up Time 4 — 5 —
6 — 5 — 6 — 7 — ns
tHCK Clock Enable, Disable Hold Time
2— 2 —
2 — 3 — 3 — 3 — ns
Port-to-Port Delay
tCWDD
Write Port Clock High to Read
Data Delay
— 30 — 35
— 45 — 35 — 45 — 55 ns
NOTES:
1. Transition is measured +/-200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3007 tbl 08
6.23 5
5 Page | ||
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| PDF Descargar | [ Datasheet IDT7099S.PDF ] | |
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