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Número de pieza | IDT72V11081L15PFI | |
Descripción | 3.3 VOLT MULTIMEDIA FIFO | |
Fabricantes | Integrated Device Technology | |
Logotipo | ||
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No Preview Available ! 3.3 VOLT MULTIMEDIA FIFO
256 x 8, 512 x 8,
1,024 x 8, 2,048 x 8,
and 4,096 x 8
IDT72V10081, IDT72V11081
IDT72V12081, IDT72V13081
IDT72V14081
FEATURES
• 256 x 8-bit organization array (IDT72V10081)
• 512 x 8-bit organization array (IDT72V11081)
• 1,024 x 8-bit organization array (IDT72V12081)
• 2,048 x 8-bit organization array (IDT72V13081)
• 4,096 x 8-bit organization array (IDT72V14081)
• 15 ns read/write cycle time
• 5V input tolerant
• Independent Read and Write clocks
• Empty and Full Flags signal FIFO status
• Output Enable puts output data bus in high-impedance state
• Available in 32-pin plastic Thin Quad FlatPack (TQFP)
• Industrial temperature range (–40°C to +85°C)
DESCRIPTION
The IDT72V10081/72V11081/72V12081/72V13081/72V14081 devices
are low-power First-In, First-Out (FIFO) memories with clocked read and write
controls. These devices have a 256, 512, 1,024, 2,048 and 4,096 x 8-bit
memory array, respectively. These FIFOs are applicable for a wide variety of
data buffering needs such as graphics and interprocessor communication.
These FIFOs have 8-bit input and output ports. The input port is
controlled by a free-running clock (WCLK) and Write Enable pin (WEN).
Data is written into the Multimedia FIFO on every rising clock edge when
the Write Enable pin is asserted. The output port is controlled by another
clock pin (RCLK) and Read Enable pin (REN). The Read Clock can be
tied to the Write Clock for single clock operation or the two clocks can run
asynchronous of one another for dual-clock operation. An Output Enable
pin (OE) is provided on the read port for three-state control of the output.
The Multimedia FIFOs have two fixed flags, Empty (EF) and Full (FF).
These FIFOs are fabricated using IDT's submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN
WRITE
CONTROL
D0 - D7
Data In
x8
FIFO ARRAY
RESET LOGIC
RS
READ
CONTROL
RCLK
REN
OE
Q0 - Q7
Data Out
x8
FLAG OUTPUTS
EF FF
6161 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-6161/2
1 page IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIALTEMPERATURERANGE
SIGNAL DESCRIPTIONS
INPUTS
DATA IN (D0 - D7)
Data inputs for 8-bit wide data.
CONTROLS
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken to a LOW state.
During reset, both internal read and write pointers are set to the first location.
A reset is required after power-up before a write operation can take place. The
Full Flag (FF) will be reset to HIGH after tRSF. The Empty Flag (EF) will be
resettoLOWaftertRSF. Duringreset,theoutputregisterisinitializedtoallzeros.
READ ENABLES (REN)
When both Read Enable (REN) is LOW, data is read from the FIFO array
to the output register on the LOW-to-HIGH transition of the Read Clock (RCLK).
When Read Enable (REN) is HIGH, the output register holds the previous
data and no new data is allowed to be loaded into the register.
When all the data has been read from the FIFO, the Empty Flag (EF) will go
LOW, inhibiting further read operations. Once a valid write operation has been
accomplished, the Empty Flag (EF) will go HIGH after tREF and a valid read
can begin. The Read Enable (REN) is ignored when the FIFO is empty.
OUTPUT ENABLE (OE)
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receive data from the output register. When Output Enable (OE) is disabled
(HIGH), the Q output data bus is in a high-impedance state.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
(WCLK). DatasetupandholdtimesmustbemetinrespecttotheLOW-to-HIGH
transition of the Write Clock (WCLK). The Full Flag (FF) is synchronized with
respect to the LOW-to-HIGH transition of the Write Clock (WCLK).
The Write and Read clocks can be asynchronous or coincident.
WRITE ENABLE (WEN)
When Write Enable (WEN) is low, data can be loaded into the input register
and FIFO array on the LOW-to-HIGH transition of every Write Clock (WCLK).
DataisstoredintheFIFO arraysequentiallyandindependentlyofanyon-going
read operation.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle, the Full Flag (FF)
will go HIGH after tWFF, allowing a valid write to begin. Write Enable (WEN)
is ignored when the FIFO is full.
OUTPUTS
FULL FLAG (FF)
The Full Flag (FF) will go LOW, inhibiting further write operation, when the
device is full. If no reads are performed after Reset (RS), the Full Flag (FF)
will go LOW after 256 writes for the IDT72V10081, 512 writes for the
IDT72V11081, 1,024 writes for the IDT72V12081, 2,048 writes for the
IDT72V13081 and 4,096 writes for the IDT72V14081.
The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH
transition of the Write Clock (WCLK).
EMPTY FLAG (EF)
The Empty Flag (EF) will go LOW, inhibiting further read operations, when
the read pointer is equal to the write pointer, indicating the device is empty.
The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH
transition of the Read Clock (RCLK).
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
Clock (RCLK). The Empty Flag (EF)is synchronized with respect to the LOW-
to-HIGH transition of the Read Clock (RCLK).
The Write and Read clocks can be asynchronous or coincident.
DATA OUTPUTS (Q0 - Q7)
Data outputs for a 8-bit wide data.
5
5 Page |
Páginas | Total 9 Páginas | |
PDF Descargar | [ Datasheet IDT72V11081L15PFI.PDF ] |
Número de pieza | Descripción | Fabricantes |
IDT72V11081L15PFI | 3.3 VOLT MULTIMEDIA FIFO | Integrated Device Technology |
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